blob: e64635f606b433103fcf9300369a86b42536c69f [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marc Jones24484842017-05-04 21:17:45 -06002
Marc Jones24484842017-05-04 21:17:45 -06003#include <device/device.h>
Marc Jones24484842017-05-04 21:17:45 -06004#include <device/pci.h>
Marc Jones24484842017-05-04 21:17:45 -06005#include <device/pci_ops.h>
Marshall Dawson25e54012019-05-29 09:29:12 -06006#include <device/pci_def.h>
Marshall Dawsonaa67def2019-05-03 16:10:34 -06007#include <amdblocks/sata.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -06008#include <soc/southbridge.h>
Marc Jones24484842017-05-04 21:17:45 -06009
Marshall Dawsonaa67def2019-05-03 16:10:34 -060010void soc_enable_sata_features(struct device *dev)
Marc Jones24484842017-05-04 21:17:45 -060011{
Marshall Dawson25e54012019-05-29 09:29:12 -060012 u8 *ahci_ptr;
13 u32 misc_ctl, cap_cfg;
Marc Jones24484842017-05-04 21:17:45 -060014
Marc Jones24484842017-05-04 21:17:45 -060015 u32 temp;
16
17 /* unlock the write-protect */
Marshall Dawson25e54012019-05-29 09:29:12 -060018 misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
19 misc_ctl |= SATA_MISC_SUBCLASS_WREN;
20 pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl);
Marc Jones24484842017-05-04 21:17:45 -060021
22 /* set the SATA AHCI mode to allow port expanders */
Marshall Dawson25e54012019-05-29 09:29:12 -060023 ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
24 pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256);
25
26 cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
27 cap_cfg |= SATA_CAPABILITY_SPM;
28 write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
Marc Jones24484842017-05-04 21:17:45 -060029
30 /* lock the write-protect */
Marshall Dawson25e54012019-05-29 09:29:12 -060031 temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
32 temp &= ~SATA_MISC_SUBCLASS_WREN;
33 pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
Marc Jones24484842017-05-04 21:17:45 -060034};