| Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* TODO: Check if this is still correct */ |
| 4 | |
| 5 | #include <amdblocks/acpimmio.h> |
| 6 | #include <amdblocks/espi.h> |
| 7 | #include <amdblocks/i2c.h> |
| 8 | #include <amdblocks/lpc.h> |
| 9 | #include <amdblocks/pmlib.h> |
| 10 | #include <amdblocks/smbus.h> |
| 11 | #include <soc/i2c.h> |
| 12 | #include <soc/southbridge.h> |
| 13 | #include <soc/uart.h> |
| 14 | |
| 15 | #include "chip.h" |
| 16 | |
| 17 | /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ |
| 18 | static const struct soc_i2c_scl_pin i2c_scl_pins[] = { |
| 19 | I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), |
| 20 | I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), |
| 21 | I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), |
| 22 | I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), |
| 23 | }; |
| 24 | |
| 25 | static void reset_i2c_peripherals(void) |
| 26 | { |
| 27 | const struct soc_amd_sabrina_config *cfg = config_of_soc(); |
| 28 | struct soc_i2c_peripheral_reset_info reset_info; |
| 29 | |
| 30 | reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; |
| 31 | reset_info.i2c_scl = i2c_scl_pins; |
| 32 | reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); |
| 33 | sb_reset_i2c_peripherals(&reset_info); |
| 34 | } |
| 35 | |
| 36 | /* Before console init */ |
| 37 | void fch_pre_init(void) |
| 38 | { |
| 39 | /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access |
| 40 | the GPIO registers. */ |
| 41 | enable_acpimmio_decode_pm04(); |
| 42 | /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ |
| 43 | lpc_early_init(); |
| 44 | |
| 45 | /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI |
| 46 | interface hasn't already been set up in verstage on PSP */ |
| 47 | if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) |
| 48 | configure_espi_with_mb_hook(); |
| 49 | |
| 50 | fch_spi_early_init(); |
| 51 | fch_smbus_init(); |
| 52 | fch_enable_cf9_io(); |
| 53 | fch_enable_legacy_io(); |
| 54 | fch_disable_legacy_dma_io(); |
| 55 | enable_aoac_devices(); |
| 56 | reset_i2c_peripherals(); |
| 57 | |
| 58 | /* |
| 59 | * On reset Range_0 defaults to enabled. We want to start with a clean |
| 60 | * slate to not have things unexpectedly enabled. |
| 61 | */ |
| 62 | clear_uart_legacy_config(); |
| 63 | |
| 64 | if (CONFIG(AMD_SOC_CONSOLE_UART)) |
| 65 | set_uart_config(CONFIG_UART_FOR_CONSOLE); |
| 66 | |
| 67 | /* disable the keyboard reset function before mainboard GPIO setup */ |
| 68 | if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) |
| 69 | fch_disable_kb_rst(); |
| 70 | } |
| 71 | |
| 72 | /* After console init */ |
| 73 | void fch_early_init(void) |
| 74 | { |
| 75 | pm_set_power_failure_state(); |
| 76 | fch_print_pmxc0_status(); |
| 77 | i2c_soc_early_init(); |
| 78 | show_spi_speeds_and_modes(); |
| 79 | |
| 80 | if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) |
| 81 | lpc_disable_spi_rom_sharing(); |
| 82 | } |