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review.coreboot.org / coreboot / 27d6299d51744bda549b7764b8fde909ad812e33 / . / src / soc / amd / sabrina / chip.h
blob: 366260596466bfe3be1de07977348d3975f72ac4 [file] [log] [blame]
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3/* TODO: Check if this is still correct */
4
5#ifndef SABRINA_CHIP_H
6#define SABRINA_CHIP_H
7
8#include <amdblocks/chip.h>
Felix Held556d1cc2022-02-02 22:11:52 +0100[diff] [blame]9#include <amdblocks/i2c.h>
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]10#include <gpio.h>
11#include <soc/i2c.h>
12#include <soc/southbridge.h>
13#include <drivers/i2c/designware/dw_i2c.h>
14#include <types.h>
15#include <vendorcode/amd/fsp/sabrina/FspUsb.h>
16
17struct soc_amd_sabrina_config {
18 struct soc_amd_common_config common_config;
19 u8 i2c_scl_reset;
20 struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
Felix Held556d1cc2022-02-02 22:11:52 +0100[diff] [blame]21 struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]22
23 /* Enable S0iX support */
24 bool s0ix_enable;
25
26 enum {
27 DOWNCORE_AUTO = 0,
28 DOWNCORE_1 = 1, /* Run with 1 physical core */
29 DOWNCORE_2 = 3, /* Run with 2 physical cores */
30 DOWNCORE_3 = 4, /* Run with 3 physical cores */
31 DOWNCORE_4 = 6, /* Run with 4 physical cores */
32 DOWNCORE_5 = 8, /* Run with 5 physical cores */
33 DOWNCORE_6 = 9, /* Run with 6 physical cores */
34 DOWNCORE_7 = 10, /* Run with 7 physical cores */
35 } downcore_mode;
36 bool disable_smt; /* disable second thread on all physical cores */
37
38 uint8_t stt_control;
39 uint8_t stt_pcb_sensor_count;
40 uint16_t stt_min_limit;
41 uint16_t stt_m1;
42 uint16_t stt_m2;
43 uint16_t stt_m3;
44 uint16_t stt_m4;
45 uint16_t stt_m5;
46 uint16_t stt_m6;
47 uint16_t stt_c_apu;
48 uint16_t stt_c_gpu;
49 uint16_t stt_c_hs2;
50 uint16_t stt_alpha_apu;
51 uint16_t stt_alpha_gpu;
52 uint16_t stt_alpha_hs2;
53 uint16_t stt_skin_temp_apu;
54 uint16_t stt_skin_temp_gpu;
55 uint16_t stt_skin_temp_hs2;
56 uint16_t stt_error_coeff;
57 uint16_t stt_error_rate_coefficient;
58
59 uint8_t stapm_boost;
60 uint32_t stapm_time_constant_s;
61 uint32_t apu_only_sppt_limit;
62 uint32_t sustained_power_limit_mW;
63 uint32_t fast_ppt_limit_mW;
64 uint32_t slow_ppt_limit_mW;
65 uint32_t slow_ppt_time_constant_s;
66 uint32_t thermctl_limit_degreeC;
67
68 uint8_t smartshift_enable;
69
70 uint8_t system_configuration;
71
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]72 /* telemetry settings */
73 uint32_t telemetry_vddcrvddfull_scale_current_mA;
74 uint32_t telemetry_vddcrvddoffset;
75 uint32_t telemetry_vddcrsocfull_scale_current_mA;
76 uint32_t telemetry_vddcrsocoffset;
77
78 /* Enable dptc for tablet mode (0 = disable, 1 = enable) */
79 uint8_t dptc_enable;
80
81 /* STAPM Configuration for tablet mode (need enable dptc_enable first) */
82 uint32_t fast_ppt_limit_tablet_mode_mW;
83 uint32_t slow_ppt_limit_tablet_mode_mW;
84 uint32_t sustained_power_limit_tablet_mode_mW;
85 uint32_t thermctl_limit_tablet_mode_degreeC;
86
87 /* The array index is the general purpose PCIe clock output number. Values in here
88 aren't the values written to the register to have the default to be always on. */
89 enum {
90 GPP_CLK_ON, /* GPP clock always on; default */
91 GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
92 GPP_CLK_OFF, /* GPP clk off */
Felix Helda05f5182022-06-10 21:04:36 +0200[diff] [blame]93 } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]94
95 /* performance policy for the PCIe links: power consumption vs. link speed */
96 enum {
97 DXIO_PSPP_DISABLED = 0,
98 DXIO_PSPP_PERFORMANCE,
99 DXIO_PSPP_BALANCED,
100 DXIO_PSPP_POWERSAVE,
101 } pspp_policy;
102
103 uint8_t usb_phy_custom;
104 struct usb_phy_config usb_phy;
105};
106
107#endif /* SABRINA_CHIP_H */