Angel Pons | 41e66ac | 2020-09-15 13:17:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef __X4X_RAMINIT_H__ |
| 4 | #define __X4X_RAMINIT_H__ |
| 5 | |
| 6 | #include <stdint.h> |
| 7 | |
| 8 | #define NOP_CMD 0x2 |
| 9 | #define PRECHARGE_CMD 0x4 |
| 10 | #define MRS_CMD 0x6 |
| 11 | #define EMRS_CMD 0x8 |
| 12 | #define EMRS1_CMD (EMRS_CMD | 0x10) |
| 13 | #define EMRS2_CMD (EMRS_CMD | 0x20) |
| 14 | #define EMRS3_CMD (EMRS_CMD | 0x30) |
| 15 | #define ZQCAL_CMD 0xa |
| 16 | #define CBR_CMD 0xc |
| 17 | #define NORMALOP_CMD 0xe |
| 18 | |
| 19 | #define TOTAL_CHANNELS 2 |
| 20 | #define TOTAL_DIMMS 4 |
| 21 | #define TOTAL_BYTELANES 8 |
| 22 | #define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) |
| 23 | #define RAW_CARD_UNPOPULATED 0xff |
| 24 | #define RAW_CARD_POPULATED 0 |
| 25 | |
| 26 | #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) |
| 27 | #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) |
| 28 | #define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ |
| 29 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ |
| 30 | !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) |
| 31 | #define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ |
| 32 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ |
| 33 | !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) |
| 34 | #define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ |
| 35 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ |
| 36 | (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) |
| 37 | #define FOR_EACH_DIMM(idx) \ |
| 38 | for (idx = 0; idx < TOTAL_DIMMS; ++idx) |
| 39 | #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ |
| 40 | FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) |
| 41 | #define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ |
| 42 | for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) |
| 43 | #define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ |
| 44 | FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) |
| 45 | #define CHANNEL_IS_POPULATED(dimms, idx) \ |
| 46 | ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ |
| 47 | || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) |
| 48 | #define CHANNEL_IS_CARDF(dimms, idx) \ |
| 49 | ((dimms[idx<<1].card_type == 0xf) \ |
| 50 | || (dimms[(idx<<1) + 1].card_type == 0xf)) |
| 51 | #define IF_CHANNEL_POPULATED(dimms, idx) \ |
| 52 | if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ |
| 53 | || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) |
| 54 | #define FOR_EACH_CHANNEL(idx) \ |
| 55 | for (idx = 0; idx < TOTAL_CHANNELS; ++idx) |
| 56 | #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ |
| 57 | FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) |
| 58 | |
| 59 | #define RANKS_PER_CHANNEL 4 |
| 60 | #define RANK_IS_POPULATED(dimms, ch, r) \ |
| 61 | (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ |
| 62 | ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) |
| 63 | #define IF_RANK_POPULATED(dimms, ch, r) \ |
| 64 | if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \ |
| 65 | && ((r) < dimms[ch<<1].ranks)) \ |
| 66 | || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \ |
| 67 | && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) |
| 68 | #define FOR_EACH_RANK_IN_CHANNEL(r) \ |
| 69 | for (r = 0; r < RANKS_PER_CHANNEL; ++r) |
| 70 | #define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ |
| 71 | FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) |
| 72 | #define FOR_EACH_RANK(ch, r) \ |
| 73 | FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) |
| 74 | #define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ |
| 75 | FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) |
| 76 | #define FOR_EACH_BYTELANE(l) \ |
| 77 | for (l = 0; l < TOTAL_BYTELANES; l++) |
| 78 | #define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \ |
| 79 | FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l) |
| 80 | |
| 81 | #define DDR3_MAX_CAS 18 |
| 82 | |
| 83 | enum fsb_clock { |
| 84 | FSB_CLOCK_800MHz = 0, |
| 85 | FSB_CLOCK_1066MHz = 1, |
| 86 | FSB_CLOCK_1333MHz = 2, |
| 87 | }; |
| 88 | |
| 89 | enum mem_clock { |
| 90 | MEM_CLOCK_400MHz = 0, |
| 91 | MEM_CLOCK_533MHz = 1, |
| 92 | MEM_CLOCK_667MHz = 2, |
| 93 | MEM_CLOCK_800MHz = 3, |
| 94 | MEM_CLOCK_1066MHz = 4, |
| 95 | MEM_CLOCK_1333MHz = 5, |
| 96 | }; |
| 97 | |
| 98 | enum ddr { |
| 99 | DDR2 = 2, |
| 100 | DDR3 = 3, |
| 101 | }; |
| 102 | |
| 103 | enum ddrxspd { |
| 104 | DDR2SPD = 0x8, |
| 105 | DDR3SPD = 0xb, |
| 106 | }; |
| 107 | |
| 108 | enum chip_width { /* as in DDR3 spd */ |
| 109 | CHIP_WIDTH_x4 = 0, |
| 110 | CHIP_WIDTH_x8 = 1, |
| 111 | CHIP_WIDTH_x16 = 2, |
| 112 | CHIP_WIDTH_x32 = 3, |
| 113 | }; |
| 114 | |
| 115 | enum chip_cap { /* as in DDR3 spd */ |
| 116 | CHIP_CAP_256M = 0, |
| 117 | CHIP_CAP_512M = 1, |
| 118 | CHIP_CAP_1G = 2, |
| 119 | CHIP_CAP_2G = 3, |
| 120 | CHIP_CAP_4G = 4, |
| 121 | CHIP_CAP_8G = 5, |
| 122 | CHIP_CAP_16G = 6, |
| 123 | }; |
| 124 | |
| 125 | struct dll_setting { |
| 126 | u8 tap; |
| 127 | u8 pi; |
| 128 | u8 db_en; |
| 129 | u8 db_sel; |
| 130 | u8 clk_delay; |
| 131 | u8 coarse; |
| 132 | }; |
| 133 | |
| 134 | struct rt_dqs_setting { |
| 135 | u8 tap; |
| 136 | u8 pi; |
| 137 | }; |
| 138 | |
| 139 | enum n_banks { |
| 140 | N_BANKS_4 = 0, |
| 141 | N_BANKS_8 = 1, |
| 142 | }; |
| 143 | |
| 144 | struct timings { |
| 145 | unsigned int CAS; |
| 146 | unsigned int tclk; |
| 147 | enum fsb_clock fsb_clk; |
| 148 | enum mem_clock mem_clk; |
| 149 | unsigned int tRAS; |
| 150 | unsigned int tRP; |
| 151 | unsigned int tRCD; |
| 152 | unsigned int tWR; |
| 153 | unsigned int tRFC; |
| 154 | unsigned int tWTR; |
| 155 | unsigned int tRRD; |
| 156 | unsigned int tRTP; |
| 157 | }; |
| 158 | |
| 159 | struct dimminfo { |
| 160 | unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */ |
| 161 | enum chip_width width; |
| 162 | unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ |
| 163 | enum n_banks n_banks; |
| 164 | unsigned int ranks; |
| 165 | unsigned int rows; |
| 166 | unsigned int cols; |
| 167 | u16 spd_crc; |
| 168 | u8 mirrored; |
| 169 | }; |
| 170 | |
| 171 | struct rcven_timings { |
| 172 | u8 min_common_coarse; |
| 173 | u8 coarse_offset[TOTAL_BYTELANES]; |
| 174 | u8 medium[TOTAL_BYTELANES]; |
| 175 | u8 tap[TOTAL_BYTELANES]; |
| 176 | u8 pi[TOTAL_BYTELANES]; |
| 177 | }; |
| 178 | |
| 179 | /* The setup is up to two DIMMs per channel */ |
| 180 | struct sysinfo { |
| 181 | int boot_path; |
| 182 | enum fsb_clock max_fsb; |
| 183 | |
| 184 | int dimm_config[2]; |
| 185 | int spd_type; |
| 186 | int channel_capacity[2]; |
| 187 | struct timings selected_timings; |
| 188 | struct dimminfo dimms[4]; |
| 189 | u8 spd_map[4]; |
| 190 | struct rcven_timings rcven_t[TOTAL_CHANNELS]; |
| 191 | /* |
| 192 | * The rt_dqs delay register for rank 0 seems to be used |
| 193 | * for all other ranks on the channel, so only save that |
| 194 | */ |
| 195 | struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][TOTAL_BYTELANES]; |
| 196 | struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; |
| 197 | struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; |
| 198 | u8 nmode; |
| 199 | u8 stacked_mode; |
| 200 | }; |
| 201 | |
| 202 | enum ddr2_signals { |
| 203 | CLKSET0 = 0, |
| 204 | CTRL0, |
| 205 | CLKSET1, |
| 206 | CMD, |
| 207 | CTRL1, |
| 208 | CTRL2, |
| 209 | CTRL3, |
| 210 | }; |
| 211 | |
| 212 | void sdram_initialize(int boot_path, const u8 *spd_map); |
| 213 | void do_raminit(struct sysinfo *, int fast_boot); |
| 214 | void rcven(struct sysinfo *s); |
| 215 | u32 fsb_to_mhz(u32 speed); |
| 216 | u32 ddr_to_mhz(u32 speed); |
| 217 | u32 test_address(int channel, int rank); |
| 218 | void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); |
| 219 | void dqset(u8 ch, u8 lane, const struct dll_setting *setting); |
| 220 | void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); |
| 221 | int do_write_training(struct sysinfo *s); |
| 222 | int do_read_training(struct sysinfo *s); |
| 223 | void search_write_leveling(struct sysinfo *s); |
| 224 | void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); |
| 225 | |
| 226 | extern const struct dll_setting default_ddr2_667_ctrl[7]; |
| 227 | extern const struct dll_setting default_ddr2_800_ctrl[7]; |
| 228 | extern const struct dll_setting default_ddr3_800_ctrl[2][7]; |
| 229 | extern const struct dll_setting default_ddr3_1067_ctrl[2][7]; |
| 230 | extern const struct dll_setting default_ddr3_1333_ctrl[2][7]; |
| 231 | extern const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES]; |
| 232 | extern const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES]; |
| 233 | extern const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES]; |
| 234 | extern const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES]; |
| 235 | extern const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES]; |
| 236 | extern const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES]; |
| 237 | extern const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES]; |
| 238 | extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES]; |
| 239 | extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES]; |
| 240 | extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES]; |
| 241 | extern const u8 ddr3_emrs1_rtt_nom_config[16][4]; |
| 242 | extern const u8 post_jedec_tab[3][4][2]; |
| 243 | extern const u32 ddr3_c2_tab[2][3][6][2]; |
| 244 | extern const u8 ddr3_c2_x264[3][6]; |
| 245 | extern const u16 ddr3_c2_x23c[3][6]; |
| 246 | |
| 247 | #endif /* __X4X_RAMINIT_H__ */ |