Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 2 | |
| 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 5 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 7 | #include <cbmem.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 8 | #include <cpu/intel/smm_reloc.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 9 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 10 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 11 | #include <program_loading.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 12 | #include "sandybridge.h" |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 13 | #include <security/intel/txt/txt_platform.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 14 | #include <stddef.h> |
| 15 | #include <stdint.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 16 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 17 | static uintptr_t northbridge_get_tseg_base(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 18 | { |
Angel Pons | 63c0dc9 | 2020-10-01 20:23:18 +0200 | [diff] [blame] | 19 | /* TSEG has 1 MiB granularity, and bit 0 is a lock */ |
| 20 | return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEGMB), 1 * MiB); |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 21 | } |
| 22 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 23 | static size_t northbridge_get_tseg_size(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 24 | { |
| 25 | return CONFIG_SMM_TSEG_SIZE; |
| 26 | } |
| 27 | |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 28 | union dpr_register txt_get_chipset_dpr(void) |
| 29 | { |
| 30 | return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) }; |
| 31 | } |
| 32 | |
| 33 | /* |
| 34 | * Return the topmost memory address below 4 GiB available for general |
| 35 | * use, from software's view of memory. Do not confuse this with TOLUD, |
| 36 | * which applies to the DRAM as viewed by the memory controller itself. |
| 37 | */ |
| 38 | static uintptr_t top_of_low_usable_memory(void) |
| 39 | { |
| 40 | /* |
| 41 | * Base of DPR is top of usable DRAM below 4 GiB. However, DPR |
| 42 | * may not always be enabled. Unlike most memory map registers, |
| 43 | * the DPR register stores top of DPR instead of its base address. |
| 44 | * Top of DPR is R/O, and mirrored from TSEG base by hardware. |
| 45 | */ |
| 46 | uintptr_t tolum = northbridge_get_tseg_base(); |
| 47 | |
| 48 | const union dpr_register dpr = txt_get_chipset_dpr(); |
| 49 | |
| 50 | /* Subtract DMA Protected Range size if enabled */ |
| 51 | if (dpr.epm) |
| 52 | tolum -= dpr.size * MiB; |
| 53 | |
| 54 | return tolum; |
| 55 | } |
| 56 | |
Angel Pons | 63c0dc9 | 2020-10-01 20:23:18 +0200 | [diff] [blame] | 57 | void *cbmem_top_chipset(void) |
| 58 | { |
Michał Żygowski | ede8718 | 2021-11-21 11:53:42 +0100 | [diff] [blame] | 59 | return (void *)top_of_low_usable_memory(); |
Angel Pons | 63c0dc9 | 2020-10-01 20:23:18 +0200 | [diff] [blame] | 60 | } |
| 61 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 62 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 63 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 64 | *start = northbridge_get_tseg_base(); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 65 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 66 | } |
| 67 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 68 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 69 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 70 | uintptr_t top_of_ram = (uintptr_t)cbmem_top(); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 71 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 72 | /* |
| 73 | * Cache 8MiB below the top of ram. On sandybridge systems the top of |
Elyes HAOUAS | ef90609 | 2020-02-20 19:41:17 +0100 | [diff] [blame] | 74 | * RAM under 4GiB is the start of the TSEG region. It is required to |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 75 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 76 | * for ramstage before setting up the entire RAM as cacheable. |
| 77 | */ |
| 78 | postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 79 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 80 | /* |
| 81 | * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 82 | * is where the TSEG region resides. However, it is not restricted |
| 83 | * to SMM mode until SMM has been relocated. By setting the region |
| 84 | * to cacheable it provides faster access when relocating the SMM |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 85 | * handler as well as using the TSEG region for other purposes. |
| 86 | */ |
| 87 | postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 88 | } |