Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 6 | #include <console/console.h> |
Angel Pons | 2f30e8c | 2020-09-16 13:29:21 +0200 | [diff] [blame] | 7 | #include <southbridge/intel/i82801ix/i82801ix.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | |
| 9 | #include "gm45.h" |
| 10 | |
| 11 | static void init_egress(void) |
| 12 | { |
| 13 | /* VC0: TC0 only */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 14 | epbar_clrbits8(EPVC0RCTL, ~1); |
| 15 | epbar_clrsetbits8(EPPVCCAP1, 7, 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 16 | |
| 17 | /* VC1: isoch */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 18 | epbar_write32(EPVC1MTS, 0x0a0a0a0a); |
| 19 | epbar_clrsetbits32(EPVC1RCAP, 127 << 16, 0x0a << 16); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 20 | |
| 21 | /* VC1: ID1, TC7 */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 22 | epbar_clrsetbits32(EPVC1RCTL, 7 << 24, 1 << 24); |
| 23 | epbar_clrsetbits8(EPVC1RCTL, ~1, 1 << 7); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 24 | |
| 25 | /* VC1 ARB table: setup and enable */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 26 | epbar_write32(EP_PORTARB(0), 0x55555555); |
| 27 | epbar_write32(EP_PORTARB(1), 0x55555555); |
| 28 | epbar_write32(EP_PORTARB(2), 0x55555555); |
| 29 | epbar_write32(EP_PORTARB(3), 0x55555555); |
| 30 | epbar_write32(EP_PORTARB(4), 0x55555555); |
| 31 | epbar_write32(EP_PORTARB(5), 0x55555555); |
| 32 | epbar_write32(EP_PORTARB(6), 0x55555555); |
| 33 | epbar_write32(EP_PORTARB(7), 0x00005555); |
| 34 | epbar_setbits32(EPVC1RCTL, 1 << 16); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 35 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 36 | while ((epbar_read8(EPVC1RSTS) & 1) != 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 37 | |
| 38 | /* VC1: enable */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 39 | epbar_setbits32(EPVC1RCTL, 1 << 31); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 40 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 41 | while ((epbar_read8(EPVC1RSTS) & 2) != 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | /* MCH side */ |
| 45 | /* b2step: b2 stepping or higher */ |
| 46 | static void init_dmi(int b2step) |
| 47 | { |
| 48 | /* VC0: TC0 only */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 49 | dmibar_clrbits8(DMIVC0RCTL, ~1); |
| 50 | dmibar_clrsetbits8(DMIPVCCAP1, 7, 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 51 | |
| 52 | /* VC1: ID1, TC7 */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 53 | dmibar_clrsetbits32(DMIVC1RCTL, 7 << 24, 1 << 24); |
| 54 | dmibar_clrsetbits8(DMIVC1RCTL, ~1, 1 << 7); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 55 | |
| 56 | /* VC1: enable */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 57 | dmibar_setbits32(DMIVC1RCTL, 1 << 31); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 58 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 59 | while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 60 | |
| 61 | /* additional configuration. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 62 | dmibar_setbits32(0x200, 3 << 13); |
| 63 | dmibar_clrbits32(0x200, 1 << 21); |
| 64 | dmibar_clrsetbits32(0x200, 3 << 26, 2 << 26); |
| 65 | dmibar_write32(0x2c, 0x86000040); |
| 66 | dmibar_setbits32(0xfc, 1 << 0); |
| 67 | dmibar_setbits32(0xfc, 1 << 1); |
| 68 | dmibar_setbits32(0xfc, 1 << 4); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 69 | if (!b2step) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 70 | dmibar_setbits32(0xfc, 1 << 11); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 71 | } else { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 72 | dmibar_clrbits32(0xfc, 1 << 11); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 73 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 74 | dmibar_clrbits32(0x204, 3 << 10); |
| 75 | dmibar_clrbits32(0xf4, 1 << 4); |
| 76 | dmibar_setbits32(0xf0, 3 << 24); |
| 77 | dmibar_write32(0xf04, 0x07050880); |
| 78 | dmibar_write32(0xf44, 0x07050880); |
| 79 | dmibar_write32(0xf84, 0x07050880); |
| 80 | dmibar_write32(0xfc4, 0x07050880); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 81 | |
| 82 | /* lock down write-once registers |
| 83 | DMIBAR32(0x84) will be set in setup_aspm(). */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 84 | dmibar_setbits32(0x308, 0); |
| 85 | dmibar_setbits32(0x314, 0); |
| 86 | dmibar_setbits32(0x324, 0); |
| 87 | dmibar_setbits32(0x328, 0); |
| 88 | dmibar_setbits32(0x334, 0); |
| 89 | dmibar_setbits32(0x338, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | static void init_pcie(const int peg_enabled, |
| 93 | const int sdvo_enabled, |
| 94 | const int peg_x16) |
| 95 | { |
Furquan Shaikh | 25f75b2 | 2016-08-29 22:51:41 -0700 | [diff] [blame] | 96 | const pci_devfn_t mch = PCI_DEV(0, 0, 0); |
| 97 | const pci_devfn_t pciex = PCI_DEV(0, 1, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 98 | |
| 99 | printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1, |
| 100 | peg_enabled?"enabled":"disabled", |
| 101 | sdvo_enabled?"enabled":"disabled"); |
| 102 | |
| 103 | if (peg_enabled) { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 104 | pci_or_config8(mch, D0F0_DEVEN, 1 << 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 105 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 106 | pci_write_config8(pciex, 0x224, |
| 107 | (pci_read_config8(pciex, 0x224) & ~31) | (peg_x16 ? 16 : 0) | 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 108 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 109 | pci_and_config16(pciex, 0x224, ~(1 << 8)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 110 | |
| 111 | /* FIXME: fill in: slot or fixed? -> devicetree */ |
| 112 | int peg_is_slot = 0; |
| 113 | if (peg_is_slot) { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 114 | pci_or_config16(pciex, PEG_CAP, 1 << 8); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | /* FIXME: fill in: slot number, slot power -> devicetree */ |
| 118 | /* Use slot number 0 by now, slots on sb count from 1. */ |
| 119 | int peg_slot = 0; /* unique within chassis */ |
| 120 | /* peg_power := val * 10^-exp */ |
| 121 | int peg_power_val = 75; |
| 122 | int peg_power_exp = 0; /* 0..3 */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 123 | const u32 tmp = (peg_slot << 17) | (peg_power_exp << 15) | (peg_power_val << 7); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 124 | pci_write_config32(pciex, SLOTCAP, tmp); |
| 125 | |
| 126 | /* GPEs */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 127 | pci_or_config8(pciex, PEGLC, 7); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 128 | |
| 129 | /* VC0: TC0 only, VC0 only */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 130 | pci_and_config8(pciex, D1F0_VC0RCTL, 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 131 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 132 | pci_and_config8(pciex, D1F0_VCCAP, ~7); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 133 | } |
| 134 | } |
| 135 | |
| 136 | static void setup_aspm(const stepping_t stepping, const int peg_enabled) |
| 137 | { |
| 138 | u32 tmp32; |
Furquan Shaikh | 25f75b2 | 2016-08-29 22:51:41 -0700 | [diff] [blame] | 139 | const pci_devfn_t pciex = PCI_DEV(0, 1, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 140 | |
| 141 | /* Prerequisites for ASPM: */ |
| 142 | if (peg_enabled) { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 143 | pci_or_config32(pciex, 0x200, 3 << 13); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 144 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 145 | pci_and_config32(pciex, 0x0f0, ~((1 << 27) | (1 << 26))); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 146 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 147 | pci_or_config32(pciex, 0x0f0, 3 << 24); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 148 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 149 | pci_and_config32(pciex, 0x0f4, ~(1 << 4)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 150 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 151 | pci_or_config32(pciex, 0x0fc, 1 << 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 152 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 153 | pci_or_config32(pciex, 0x0fc, 1 << 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 154 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 155 | pci_or_config32(pciex, 0x0fc, 1 << 4); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 156 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 157 | pci_and_config32(pciex, 0x0fc, ~(7 << 5)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 158 | |
| 159 | /* Set L0s, L1 supported in LCTL? */ |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 160 | pci_or_config32(pciex, 0x0b0, 3 << 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 161 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 162 | pci_or_config32(pciex, 0x0f0, 3 << 24); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 163 | |
| 164 | tmp32 = pci_read_config32(pciex, 0x0f0); |
| 165 | if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1)) |
| 166 | tmp32 |= (1 << 31); |
| 167 | else if (stepping >= STEPPING_B2) |
| 168 | tmp32 &= ~(1 << 31); |
| 169 | pci_write_config32(pciex, 0x0f0, tmp32); |
| 170 | |
| 171 | tmp32 = pci_read_config32(pciex, 0x0fc); |
| 172 | if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1)) |
| 173 | tmp32 |= (1 << 10); |
| 174 | else if (stepping >= STEPPING_B2) |
| 175 | tmp32 &= ~(1 << 10); |
| 176 | pci_write_config32(pciex, 0x0fc, tmp32); |
| 177 | |
| 178 | tmp32 = pci_read_config32(pciex, 0x0fc); |
| 179 | if (stepping >= STEPPING_B2) |
| 180 | tmp32 |= (1 << 14); |
| 181 | pci_write_config32(pciex, 0x0fc, tmp32); |
| 182 | |
| 183 | tmp32 = pci_read_config32(pciex, 0x0fc); |
| 184 | if (stepping >= STEPPING_B1) |
| 185 | tmp32 &= ~(1 << 13); |
| 186 | pci_write_config32(pciex, 0x0fc, tmp32); |
| 187 | } |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 188 | dmibar_setbits8(0x0e1c, 1 << 0); |
| 189 | dmibar_setbits16(0x0f00, 3 << 8); |
| 190 | dmibar_setbits16(0x0f00, 7 << 3); |
| 191 | dmibar_clrbits32(0x0f14, 1 << 17); |
| 192 | dmibar_clrbits16(0x0e1c, 1 << 8); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 193 | if (stepping >= STEPPING_B0) { |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 194 | dmibar_clrsetbits32(0x0e28 + 4, 0xf << (52 - 32), 0xd << (52 - 32)); |
| 195 | dmibar_write32(0x0e2c, 0x88d07333); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 196 | } |
| 197 | if (peg_enabled) { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 198 | pci_and_config32(pciex, 0xa08, ~(1 << 15)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 199 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 200 | pci_or_config32(pciex, 0xa84, 1 << 8); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 201 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 202 | pci_and_config32(pciex, 0xb14, ~(1 << 17)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 203 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 204 | pci_or_config32(pciex, 0xb00, 3 << 8); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 205 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 206 | pci_or_config32(pciex, 0xb00, 7 << 3); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 207 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 208 | pci_and_config32(pciex, 0xa84, ~(1 << 8)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 209 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 210 | pci_or_config32(pciex, 0xa84, 1 << 8); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 211 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 212 | pci_update_config32(pciex, 0xb04, ~(0x1f << 23), 0x0e << 23); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 213 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 214 | pci_or_config32(pciex, 0xb04, 1 << 31); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 215 | |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 216 | pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 217 | } |
| 218 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 219 | /*\ Setup ASPM on DMI \*/ |
| 220 | |
| 221 | /* Exit latencies should be checked to be supported by |
| 222 | the endpoint (ICH), but ICH doesn't give any limits. */ |
| 223 | |
| 224 | if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 225 | dmibar_setbits8(DMILCTL, 3 << 0); // enable ASPM L0s, L1 (write-once) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 226 | else |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 227 | dmibar_setbits8(DMILCTL, 1 << 0); // enable ASPM L0s (write-once) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 228 | /* timing */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 229 | dmibar_clrsetbits32(DMILCAP, 63 << 12, 2 << 12 | 2 << 15); |
| 230 | dmibar_write8(0x208 + 3, 0); |
| 231 | dmibar_clrbits32(0x208, 3 << 20); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 232 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 233 | /*\ Setup ASPM on PEG \*/ |
| 234 | /* |
| 235 | * Maybe we just have to advertise ASPM through LCAP[11:10] |
| 236 | * (LCAP[17:15] == 010b is the default, will be locked, as it's R/WO), |
| 237 | * set 0x208[31:24,23:22] to zero, 0x224[24:21] = 1 and let the |
Martin Roth | 0cd338e | 2016-07-29 14:07:30 -0600 | [diff] [blame] | 238 | * generic ASPM code do the rest? - Nico |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 239 | */ |
| 240 | /* TODO: Prepare PEG for ASPM. */ |
| 241 | } |
| 242 | |
| 243 | static void setup_rcrb(const int peg_enabled) |
| 244 | { |
| 245 | /*\ RCRB setup: Egress Port \*/ |
| 246 | |
| 247 | /* Set component ID of MCH (1). */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 248 | epbar_write8(EPESD + 2, 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 249 | |
| 250 | /* Link1: component ID 1, link valid. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 251 | epbar_clrsetbits32(EPLE1D, 0xffffff, 1 << 16 | 1 << 0); |
| 252 | epbar_write32(EPLE1A, CONFIG_FIXED_DMIBAR_MMIO_BASE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 253 | |
| 254 | if (peg_enabled) |
| 255 | /* Link2: link_valid. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 256 | epbar_setbits8(EPLE2D, 1 << 0); /* link valid */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 257 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 258 | /*\ RCRB setup: DMI Port \*/ |
| 259 | |
| 260 | /* Set component ID of MCH (1). */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 261 | dmibar_write8(DMIESD + 2, 1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 262 | |
| 263 | /* Link1: target port 0, component id 2 (ICH), link valid. */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 264 | dmibar_write32(DMILE1D, 0 << 24 | 2 << 16 | 1 << 0); |
| 265 | dmibar_write32(DMILE1A, CONFIG_FIXED_RCBA_MMIO_BASE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 266 | |
| 267 | /* Link2: component ID 1 (MCH), link valid */ |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 268 | dmibar_clrsetbits32(DMILE2D, 0xffffff, 1 << 16 | 1 << 0); |
| 269 | dmibar_write32(DMILE2A, CONFIG_FIXED_MCHBAR_MMIO_BASE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 270 | } |
| 271 | |
| 272 | void gm45_late_init(const stepping_t stepping) |
| 273 | { |
Furquan Shaikh | 25f75b2 | 2016-08-29 22:51:41 -0700 | [diff] [blame] | 274 | const pci_devfn_t mch = PCI_DEV(0, 0, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 275 | const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 276 | const int sdvo_enabled = mchbar_read16(0x40) >> 8 & 1; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 277 | const int peg_x16 = (peg_enabled && !sdvo_enabled); |
| 278 | |
| 279 | init_egress(); |
| 280 | init_dmi(stepping >= STEPPING_B2); |
| 281 | init_pcie(peg_enabled, sdvo_enabled, peg_x16); |
| 282 | |
| 283 | setup_aspm(stepping, peg_enabled); |
| 284 | setup_rcrb(peg_enabled); |
| 285 | } |