Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 4 | #include <console/console.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <device/pci_ids.h> |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 8 | #include <drivers/intel/gma/edid.h> |
| 9 | #include <drivers/intel/gma/opregion.h> |
| 10 | #include <drivers/intel/gma/libgfxinit.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 11 | #include <string.h> |
| 12 | #include <device/pci_ops.h> |
Arthur Heymans | c51522f | 2016-08-27 01:09:19 +0200 | [diff] [blame] | 13 | #include <commonlib/helpers.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 14 | #include <types.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 15 | |
| 16 | #include "drivers/intel/gma/i915_reg.h" |
| 17 | #include "chip.h" |
| 18 | #include "gm45.h" |
Vladimir Serbinenko | 8801011 | 2014-08-16 03:35:33 +0200 | [diff] [blame] | 19 | |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 20 | static struct resource *gtt_res = NULL; |
| 21 | |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 22 | u32 gtt_read(u32 reg) |
| 23 | { |
| 24 | return read32(res2mmio(gtt_res, reg, 0)); |
| 25 | } |
| 26 | |
Vladimir Serbinenko | 8801011 | 2014-08-16 03:35:33 +0200 | [diff] [blame] | 27 | void gtt_write(u32 reg, u32 data) |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 28 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 29 | write32(res2mmio(gtt_res, reg, 0), data); |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 30 | } |
| 31 | |
Nico Huber | d85a71a | 2016-11-27 14:43:12 +0100 | [diff] [blame] | 32 | static u32 get_cdclk(struct device *const dev) |
| 33 | { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 34 | const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK; |
| 35 | |
Angel Pons | 3f1f8ef | 2021-03-27 13:52:43 +0100 | [diff] [blame] | 36 | switch (mchbar_read8(HPLLVCO_MCHBAR) & 0x7) { |
Nico Huber | d85a71a | 2016-11-27 14:43:12 +0100 | [diff] [blame] | 37 | case VCO_2666: |
| 38 | case VCO_4000: |
| 39 | case VCO_5333: |
| 40 | return cdclk_sel ? 333333333 : 222222222; |
| 41 | case VCO_3200: |
| 42 | return cdclk_sel ? 320000000 : 228571429; |
| 43 | default: |
| 44 | printk(BIOS_WARNING, |
| 45 | "Unknown VCO frequency, using default cdclk.\n"); |
| 46 | return 222222222; |
| 47 | } |
| 48 | } |
| 49 | |
Arthur Heymans | 12bed26 | 2016-11-24 13:23:05 +0100 | [diff] [blame] | 50 | static u32 freq_to_blc_pwm_ctl(struct device *const dev, |
| 51 | u16 pwm_freq, u8 duty_perc) |
| 52 | { |
| 53 | u32 blc_mod; |
| 54 | |
| 55 | blc_mod = get_cdclk(dev) / (128 * pwm_freq); |
| 56 | |
| 57 | if (duty_perc <= 100) |
| 58 | return (blc_mod << 16) | (blc_mod * duty_perc / 100); |
| 59 | else |
| 60 | return (blc_mod << 16) | blc_mod; |
| 61 | } |
| 62 | |
Arthur Heymans | 4d2d171 | 2018-11-29 12:25:31 +0100 | [diff] [blame] | 63 | u16 get_blc_pwm_freq_value(const char *edid_ascii_string) |
Arthur Heymans | c679b1f | 2018-11-29 12:21:12 +0100 | [diff] [blame] | 64 | { |
| 65 | static u16 blc_pwm_freq; |
| 66 | const struct blc_pwm_t *blc_pwm; |
| 67 | int i; |
| 68 | int blc_array_len; |
| 69 | |
| 70 | if (blc_pwm_freq > 0) |
| 71 | return blc_pwm_freq; |
| 72 | |
| 73 | blc_array_len = get_blc_values(&blc_pwm); |
| 74 | /* Find EDID string and pwm freq in lookup table */ |
| 75 | for (i = 0; i < blc_array_len; i++) { |
| 76 | if (!strcmp(blc_pwm[i].ascii_string, edid_ascii_string)) { |
| 77 | blc_pwm_freq = blc_pwm[i].pwm_freq; |
| 78 | printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", |
| 79 | blc_pwm[i].ascii_string, blc_pwm_freq); |
| 80 | break; |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | if (i == blc_array_len) |
| 85 | printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" |
| 86 | "lookup table.\n You may have issues with your panels" |
| 87 | "backlight.\n If you want to help improving coreboot" |
| 88 | "please report: this EDID string\n and the result" |
| 89 | "of `intel_read read BLC_PWM_CTL`" |
| 90 | "(from intel-gpu-tools)\n while running vendor BIOS\n", |
| 91 | edid_ascii_string); |
| 92 | |
| 93 | return blc_pwm_freq; |
| 94 | } |
| 95 | |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 96 | static void gma_pm_init_post_vbios(struct device *const dev, |
| 97 | const char *edid_ascii_string) |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 98 | { |
| 99 | const struct northbridge_intel_gm45_config *const conf = dev->chip_info; |
| 100 | |
| 101 | u32 reg32; |
Arthur Heymans | 12bed26 | 2016-11-24 13:23:05 +0100 | [diff] [blame] | 102 | u8 reg8; |
Arthur Heymans | c679b1f | 2018-11-29 12:21:12 +0100 | [diff] [blame] | 103 | u16 pwm_freq; |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 104 | |
| 105 | /* Setup Panel Power On Delays */ |
| 106 | reg32 = gtt_read(PP_ON_DELAYS); |
| 107 | if (!reg32) { |
| 108 | reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 109 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 110 | gtt_write(PP_ON_DELAYS, reg32); |
| 111 | } |
| 112 | |
| 113 | /* Setup Panel Power Off Delays */ |
| 114 | reg32 = gtt_read(PP_OFF_DELAYS); |
| 115 | if (!reg32) { |
| 116 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 117 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 118 | gtt_write(PP_OFF_DELAYS, reg32); |
| 119 | } |
| 120 | |
| 121 | /* Setup Panel Power Cycle Delay */ |
| 122 | if (conf->gpu_panel_power_cycle_delay) { |
Nico Huber | d85a71a | 2016-11-27 14:43:12 +0100 | [diff] [blame] | 123 | reg32 = (get_cdclk(dev) / 20000 - 1) |
| 124 | << PP_REFERENCE_DIVIDER_SHIFT; |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 125 | reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; |
| 126 | gtt_write(PP_DIVISOR, reg32); |
| 127 | } |
| 128 | |
| 129 | /* Enable Backlight */ |
| 130 | gtt_write(BLC_PWM_CTL2, (1 << 31)); |
Arthur Heymans | 12bed26 | 2016-11-24 13:23:05 +0100 | [diff] [blame] | 131 | reg8 = 100; |
| 132 | if (conf->duty_cycle != 0) |
| 133 | reg8 = conf->duty_cycle; |
Arthur Heymans | c679b1f | 2018-11-29 12:21:12 +0100 | [diff] [blame] | 134 | pwm_freq = get_blc_pwm_freq_value(edid_ascii_string); |
| 135 | if (pwm_freq == 0 && conf->default_pwm_freq != 0) |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 136 | pwm_freq = conf->default_pwm_freq; |
| 137 | |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 138 | if (pwm_freq == 0) |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 139 | gtt_write(BLC_PWM_CTL, 0x06100610); |
| 140 | else |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 141 | gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, pwm_freq, |
| 142 | reg8)); |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 143 | } |
| 144 | |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 145 | static void gma_func0_init(struct device *dev) |
| 146 | { |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 147 | u8 *mmio; |
| 148 | u8 edid_data_lvds[128]; |
| 149 | struct edid edid_lvds; |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 150 | const struct northbridge_intel_gm45_config *const conf = dev->chip_info; |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 151 | |
Nico Huber | f2a0be2 | 2020-04-26 17:01:25 +0200 | [diff] [blame] | 152 | intel_gma_init_igd_opregion(); |
| 153 | |
Angel Pons | 536d36a | 2021-11-03 13:13:00 +0100 | [diff] [blame] | 154 | gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 155 | if (gtt_res == NULL) |
| 156 | return; |
| 157 | mmio = res2mmio(gtt_res, 0, 0); |
Timothy Pearson | e7f7090 | 2015-04-06 22:01:23 -0500 | [diff] [blame] | 158 | |
Arthur Heymans | cc0b452 | 2022-05-06 17:04:41 +0200 | [diff] [blame] | 159 | /* |
| 160 | * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M |
| 161 | * cycles are simply not decoded which is fine. |
| 162 | */ |
| 163 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
| 164 | memset(mmio + 2 * MiB, 0, 2 * MiB); |
| 165 | |
| 166 | if (CONFIG(NO_GFX_INIT)) |
| 167 | pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 168 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 169 | if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
Nico Huber | ee352cd | 2016-01-09 23:15:53 +0100 | [diff] [blame] | 170 | /* PCI Init, will run VBIOS */ |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 171 | printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n"); |
Nico Huber | ee352cd | 2016-01-09 23:15:53 +0100 | [diff] [blame] | 172 | pci_dev_init(dev); |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 173 | } |
| 174 | |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 175 | printk(BIOS_DEBUG, "LVDS EDID\n"); |
Arthur Heymans | 8da2286 | 2017-08-06 15:56:30 +0200 | [diff] [blame] | 176 | intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_PANEL, 0x50, |
| 177 | edid_data_lvds, sizeof(edid_data_lvds)); |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 178 | intel_gmbus_stop(mmio + GMBUS0); |
| 179 | decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds); |
| 180 | |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 181 | /* Post VBIOS init */ |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 182 | gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 183 | |
Arthur Heymans | 29e5358 | 2019-10-12 17:39:31 +0200 | [diff] [blame] | 184 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && !acpi_is_wakeup_s3()) { |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 185 | int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; |
| 186 | if (vga_disable) { |
| 187 | printk(BIOS_INFO, |
| 188 | "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); |
| 189 | } else { |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 190 | int lightup_ok; |
| 191 | gma_gfxinit(&lightup_ok); |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 192 | /* Linux relies on VBT for panel info. */ |
| 193 | generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 194 | } |
Nico Huber | f2dd049 | 2017-10-29 15:42:44 +0100 | [diff] [blame] | 195 | } |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 196 | } |
| 197 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 198 | static void gma_generate_ssdt(const struct device *device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 199 | { |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 200 | const struct northbridge_intel_gm45_config *chip = device->chip_info; |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 201 | |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 202 | drivers_intel_gma_displays_ssdt_generate(&chip->gfx); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 203 | } |
| 204 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 205 | static const char *gma_acpi_name(const struct device *dev) |
| 206 | { |
| 207 | return "GFX0"; |
| 208 | } |
| 209 | |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 210 | static struct device_operations gma_func0_ops = { |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 211 | .read_resources = pci_dev_read_resources, |
| 212 | .set_resources = pci_dev_set_resources, |
| 213 | .enable_resources = pci_dev_enable_resources, |
| 214 | .acpi_fill_ssdt = gma_generate_ssdt, |
| 215 | .init = gma_func0_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 216 | .ops_pci = &pci_dev_ops_pci, |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 217 | .acpi_name = gma_acpi_name, |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 218 | }; |
| 219 | |
| 220 | static const unsigned short pci_device_ids[] = |
| 221 | { |
| 222 | 0x2a42, 0 |
| 223 | }; |
| 224 | |
| 225 | static const struct pci_driver gma __pci_driver = { |
| 226 | .ops = &gma_func0_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 227 | .vendor = PCI_VID_INTEL, |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 228 | .devices = pci_device_ids, |
| 229 | }; |