Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
| 3 | # EMMC Tx CMD Delay |
| 4 | # Refer to EDS-Vol2-16.32. |
| 5 | # [14:8] steps of delay for DDR mode, each 125ps. |
| 6 | # [6:0] steps of delay for SDR mode, each 125ps. |
| 7 | register "emmc_tx_cmd_cntl" = "0x505" |
| 8 | |
| 9 | # EMMC TX DATA Delay 1 |
| 10 | # Refer to EDS-Vol2-16.33. |
| 11 | # [14:8] steps of delay for HS400, each 125ps. |
| 12 | # [6:0] steps of delay for SDR104/HS200, each 125ps. |
| 13 | register "emmc_tx_data_cntl1" = "0x0b0c" |
| 14 | |
| 15 | # EMMC TX DATA Delay 2 |
| 16 | # Refer to EDS-Vol2-16.34. |
| 17 | # [30:24] steps of delay for SDR50, each 125ps. |
| 18 | # [22:16] steps of delay for DDR50, each 125ps. |
| 19 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 20 | # [6:0] steps of delay for SDR12, each 125ps. |
| 21 | register "emmc_tx_data_cntl2" = "0x1c282929" |
| 22 | |
| 23 | # EMMC RX CMD/DATA Delay 1 |
| 24 | # Refer to EDS-Vol2-16.35. |
| 25 | # [30:24] steps of delay for SDR50, each 125ps. |
| 26 | # [22:16] steps of delay for DDR50, each 125ps. |
| 27 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 28 | # [6:0] steps of delay for SDR12, each 125ps. |
| 29 | register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" |
| 30 | |
| 31 | # EMMC RX CMD/DATA Delay 2 |
| 32 | # Refer to EDS-Vol2-16.37. |
| 33 | # [17:16] stands for Rx Clock before Output Buffer |
| 34 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps. |
| 35 | # [6:0] steps of delay for HS200, each 125ps. |
| 36 | register "emmc_rx_cmd_data_cntl2" = "0x10028" |
| 37 | |
| 38 | # EMMC Rx Strobe Delay |
| 39 | # Refer to EDS-Vol2-16.36. |
| 40 | # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. |
| 41 | # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. |
| 42 | register "emmc_rx_strobe_cntl" = "0x0b0b" |
| 43 | |
| 44 | # Intel Common SoC Config |
| 45 | #+-------------------+---------------------------+ |
| 46 | #| Field | Value | |
| 47 | #+-------------------+---------------------------+ |
| 48 | #| GSPI0 | cr50 TPM. Early init is | |
| 49 | #| | required to set up a BAR | |
| 50 | #| | for TPM communication | |
| 51 | #| | before memory is up | |
| 52 | #| I2C5 | Audio | |
| 53 | #| I2C6 | Trackpad | |
| 54 | #+-------------------+---------------------------+ |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame] | 55 | register "tcc_offset" = "15" |
Hash.Hung | e653ad0 | 2020-01-22 14:36:38 +0800 | [diff] [blame] | 56 | |
Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 57 | register "common_soc_config" = "{ |
| 58 | .gspi[0] = { |
| 59 | .speed_mhz = 1, |
| 60 | .early_init = 1, |
| 61 | }, |
| 62 | .i2c[5] = { |
| 63 | .speed = I2C_SPEED_FAST, |
| 64 | .rise_time_ns = 104, |
| 65 | .fall_time_ns = 52, |
| 66 | }, |
| 67 | .i2c[6] = { |
| 68 | .speed = I2C_SPEED_FAST, |
| 69 | .rise_time_ns = 66, |
| 70 | .fall_time_ns = 90, |
| 71 | .data_hold_time_ns = 350, |
| 72 | }, |
| 73 | }" |
| 74 | |
| 75 | device domain 0 on |
| 76 | device pci 17.1 on |
| 77 | chip drivers/i2c/da7219 |
| 78 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" |
| 79 | register "btn_cfg" = "50" |
| 80 | register "mic_det_thr" = "500" |
| 81 | register "jack_ins_deb" = "20" |
| 82 | register "jack_det_rate" = ""32ms_64ms"" |
| 83 | register "jack_rem_deb" = "1" |
| 84 | register "a_d_btn_thr" = "0xa" |
| 85 | register "d_b_btn_thr" = "0x16" |
| 86 | register "b_c_btn_thr" = "0x21" |
| 87 | register "c_mic_btn_thr" = "0x3e" |
| 88 | register "btn_avg" = "4" |
| 89 | register "adc_1bit_rpt" = "1" |
| 90 | register "micbias_lvl" = "2600" |
| 91 | register "mic_amp_in_sel" = ""diff"" |
| 92 | device i2c 1a on end |
| 93 | end |
| 94 | end # - I2C 5 |
| 95 | device pci 17.2 on |
| 96 | chip drivers/i2c/generic |
| 97 | register "hid" = ""ELAN0000"" |
| 98 | register "desc" = ""ELAN Touchpad"" |
Matt DeVillier | dc80745 | 2022-03-30 12:30:21 -0500 | [diff] [blame] | 99 | register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" |
Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 100 | register "wake" = "GPE0_DW3_27" |
Matt DeVillier | 2cf52d8 | 2022-09-01 15:09:24 -0500 | [diff] [blame] | 101 | register "detect" = "1" |
Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 102 | device i2c 15 on end |
| 103 | end |
| 104 | chip drivers/i2c/hid |
Matt DeVillier | 2793716 | 2022-12-19 15:15:52 -0600 | [diff] [blame^] | 105 | register "generic.hid" = ""SYNA0000"" |
| 106 | register "generic.cid" = ""ACPI0C50"" |
Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 107 | register "generic.desc" = ""Synaptics Touchpad"" |
Karthikeyan Ramasubramanian | 61a5391 | 2020-11-10 14:37:38 -0700 | [diff] [blame] | 108 | register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" |
Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 109 | register "generic.wake" = "GPE0_DW3_27" |
Matt DeVillier | 2cf52d8 | 2022-09-01 15:09:24 -0500 | [diff] [blame] | 110 | register "generic.detect" = "1" |
Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 111 | register "hid_desc_reg_offset" = "0x20" |
| 112 | device i2c 0x2c on end |
| 113 | end |
| 114 | end # - I2C 6 |
| 115 | end |
Julia Tsai | 9e0dd9a | 2020-03-27 15:52:30 +0800 | [diff] [blame] | 116 | |
| 117 | # Disable compliance mode |
| 118 | |
| 119 | register "DisableComplianceMode" = "1" |
Hash.Hung | 41fe62b | 2019-11-26 23:36:40 +0800 | [diff] [blame] | 120 | end |