Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpi_gnvs.h> |
| 5 | #include <acpi/acpigen.h> |
Arthur Heymans | d90154c | 2022-12-02 13:27:35 +0100 | [diff] [blame] | 6 | #include <arch/ioapic.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 7 | #include <device/mmio.h> |
| 8 | #include <arch/smp/mpspec.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 9 | #include <console/console.h> |
| 10 | #include <device/device.h> |
| 11 | #include <device/pci_ops.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 12 | #include <intelblocks/cpulib.h> |
| 13 | #include <intelblocks/pmclib.h> |
| 14 | #include <intelblocks/acpi.h> |
| 15 | #include <soc/cpu.h> |
| 16 | #include <soc/iomap.h> |
| 17 | #include <soc/nvs.h> |
| 18 | #include <soc/pci_devs.h> |
| 19 | #include <soc/pm.h> |
| 20 | #include <soc/soc_chip.h> |
| 21 | #include <soc/systemagent.h> |
Tarun Tuli | c66ea98 | 2022-05-03 20:35:47 +0000 | [diff] [blame] | 22 | #include <cpu/cpu.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 23 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * List of supported C-states in this processor. |
| 27 | */ |
| 28 | enum { |
| 29 | C_STATE_C0, /* 0 */ |
| 30 | C_STATE_C1, /* 1 */ |
| 31 | C_STATE_C1E, /* 2 */ |
| 32 | C_STATE_C6_SHORT_LAT, /* 3 */ |
| 33 | C_STATE_C6_LONG_LAT, /* 4 */ |
| 34 | C_STATE_C7_SHORT_LAT, /* 5 */ |
| 35 | C_STATE_C7_LONG_LAT, /* 6 */ |
| 36 | C_STATE_C7S_SHORT_LAT, /* 7 */ |
| 37 | C_STATE_C7S_LONG_LAT, /* 8 */ |
| 38 | C_STATE_C8, /* 9 */ |
| 39 | C_STATE_C9, /* 10 */ |
| 40 | C_STATE_C10, /* 11 */ |
| 41 | NUM_C_STATES |
| 42 | }; |
| 43 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 44 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 45 | [C_STATE_C0] = {}, |
| 46 | [C_STATE_C1] = { |
| 47 | .latency = C1_LATENCY, |
| 48 | .power = C1_POWER, |
| 49 | .resource = MWAIT_RES(0, 0), |
| 50 | }, |
| 51 | [C_STATE_C1E] = { |
| 52 | .latency = C1_LATENCY, |
| 53 | .power = C1_POWER, |
| 54 | .resource = MWAIT_RES(0, 1), |
| 55 | }, |
| 56 | [C_STATE_C6_SHORT_LAT] = { |
| 57 | .latency = C6_LATENCY, |
| 58 | .power = C6_POWER, |
| 59 | .resource = MWAIT_RES(2, 0), |
| 60 | }, |
| 61 | [C_STATE_C6_LONG_LAT] = { |
| 62 | .latency = C6_LATENCY, |
| 63 | .power = C6_POWER, |
| 64 | .resource = MWAIT_RES(2, 1), |
| 65 | }, |
| 66 | [C_STATE_C7_SHORT_LAT] = { |
| 67 | .latency = C7_LATENCY, |
| 68 | .power = C7_POWER, |
| 69 | .resource = MWAIT_RES(3, 0), |
| 70 | }, |
| 71 | [C_STATE_C7_LONG_LAT] = { |
| 72 | .latency = C7_LATENCY, |
| 73 | .power = C7_POWER, |
| 74 | .resource = MWAIT_RES(3, 1), |
| 75 | }, |
| 76 | [C_STATE_C7S_SHORT_LAT] = { |
| 77 | .latency = C7_LATENCY, |
| 78 | .power = C7_POWER, |
| 79 | .resource = MWAIT_RES(3, 2), |
| 80 | }, |
| 81 | [C_STATE_C7S_LONG_LAT] = { |
| 82 | .latency = C7_LATENCY, |
| 83 | .power = C7_POWER, |
| 84 | .resource = MWAIT_RES(3, 3), |
| 85 | }, |
| 86 | [C_STATE_C8] = { |
| 87 | .latency = C8_LATENCY, |
| 88 | .power = C8_POWER, |
| 89 | .resource = MWAIT_RES(4, 0), |
| 90 | }, |
| 91 | [C_STATE_C9] = { |
| 92 | .latency = C9_LATENCY, |
| 93 | .power = C9_POWER, |
| 94 | .resource = MWAIT_RES(5, 0), |
| 95 | }, |
| 96 | [C_STATE_C10] = { |
| 97 | .latency = C10_LATENCY, |
| 98 | .power = C10_POWER, |
| 99 | .resource = MWAIT_RES(6, 0), |
| 100 | }, |
| 101 | }; |
| 102 | |
| 103 | static int cstate_set_non_s0ix[] = { |
| 104 | C_STATE_C1, |
| 105 | C_STATE_C6_LONG_LAT, |
| 106 | C_STATE_C7S_LONG_LAT |
| 107 | }; |
| 108 | |
| 109 | static int cstate_set_s0ix[] = { |
| 110 | C_STATE_C1, |
Bernardo Perez Priego | b4a09c0 | 2021-06-21 10:49:47 -0700 | [diff] [blame] | 111 | C_STATE_C6_LONG_LAT, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 112 | C_STATE_C10 |
| 113 | }; |
| 114 | |
Angel Pons | e9f10ff | 2021-10-17 13:28:23 +0200 | [diff] [blame] | 115 | const acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 116 | { |
| 117 | static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), |
| 118 | ARRAY_SIZE(cstate_set_non_s0ix))]; |
| 119 | int *set; |
| 120 | int i; |
| 121 | |
| 122 | config_t *config = config_of_soc(); |
| 123 | |
| 124 | int is_s0ix_enable = config->s0ix_enable; |
| 125 | |
| 126 | if (is_s0ix_enable) { |
| 127 | *entries = ARRAY_SIZE(cstate_set_s0ix); |
| 128 | set = cstate_set_s0ix; |
| 129 | } else { |
| 130 | *entries = ARRAY_SIZE(cstate_set_non_s0ix); |
| 131 | set = cstate_set_non_s0ix; |
| 132 | } |
| 133 | |
| 134 | for (i = 0; i < *entries; i++) { |
Angel Pons | 14643b3 | 2021-10-17 13:21:05 +0200 | [diff] [blame] | 135 | map[i] = cstate_map[set[i]]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 136 | map[i].ctype = i + 1; |
| 137 | } |
| 138 | return map; |
| 139 | } |
| 140 | |
| 141 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 142 | { |
| 143 | config_t *config = config_of_soc(); |
| 144 | |
| 145 | if (config->eist_enable) |
| 146 | /* Generate P-state tables */ |
| 147 | generate_p_state_entries(core_id, cores_per_package); |
| 148 | } |
| 149 | |
| 150 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 151 | { |
| 152 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 153 | |
| 154 | config_t *config = config_of_soc(); |
| 155 | |
| 156 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 157 | fadt->pm_tmr_len = 4; |
Kyösti Mälkki | 88decca | 2023-04-28 07:04:34 +0300 | [diff] [blame] | 158 | |
| 159 | fill_fadt_extended_pm_io(fadt); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 160 | |
| 161 | if (config->s0ix_enable) |
| 162 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
| 163 | } |
| 164 | |
Eran Mitrani | 4c9440c | 2022-11-29 17:46:38 -0800 | [diff] [blame] | 165 | static struct min_sleep_state min_pci_sleep_states[] = { |
| 166 | { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, |
| 167 | { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 }, |
| 168 | { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, |
Matt DeVillier | 277f36f | 2023-11-02 15:22:59 -0500 | [diff] [blame^] | 169 | { SA_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 }, |
Eran Mitrani | 4c9440c | 2022-11-29 17:46:38 -0800 | [diff] [blame] | 170 | { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, |
| 171 | { SA_DEVFN_CPU_PCIE6_0, ACPI_DEVICE_SLEEP_D3 }, |
| 172 | { SA_DEVFN_CPU_PCIE6_2, ACPI_DEVICE_SLEEP_D3 }, |
| 173 | { SA_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 }, |
| 174 | { SA_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 }, |
| 175 | { SA_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 }, |
| 176 | { SA_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 }, |
| 177 | { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, |
| 178 | { SA_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 }, |
| 179 | { SA_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, |
| 180 | { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, |
| 181 | { SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 }, |
| 182 | { SA_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, |
| 183 | { PCH_DEVFN_I2C6, ACPI_DEVICE_SLEEP_D3 }, |
| 184 | { PCH_DEVFN_I2C7, ACPI_DEVICE_SLEEP_D3 }, |
| 185 | { PCH_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 }, |
| 186 | { PCH_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 }, |
| 187 | { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, |
| 188 | { PCH_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, |
| 189 | { PCH_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 }, |
| 190 | { PCH_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 }, |
| 191 | { PCH_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, |
| 192 | { PCH_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, |
| 193 | { PCH_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, |
| 194 | { PCH_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, |
| 195 | { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, |
| 196 | { PCH_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 }, |
| 197 | { PCH_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, |
| 198 | { PCH_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, |
| 199 | { PCH_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, |
| 200 | { PCH_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, |
| 201 | { PCH_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, |
| 202 | { PCH_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, |
| 203 | { PCH_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, |
| 204 | { PCH_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, |
| 205 | { PCH_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, |
| 206 | { PCH_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, |
| 207 | { PCH_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, |
| 208 | { PCH_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, |
| 209 | { PCH_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, |
| 210 | { PCH_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, |
| 211 | { PCH_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, |
| 212 | { PCH_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, |
| 213 | { PCH_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, |
| 214 | { PCH_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, |
| 215 | { PCH_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, |
| 216 | { PCH_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, |
| 217 | { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, |
| 218 | { PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, |
| 219 | { PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, |
| 220 | { PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, |
Tarun Tuli | c66ea98 | 2022-05-03 20:35:47 +0000 | [diff] [blame] | 221 | }; |
| 222 | |
Eran Mitrani | 4c9440c | 2022-11-29 17:46:38 -0800 | [diff] [blame] | 223 | struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) |
Tarun Tuli | c66ea98 | 2022-05-03 20:35:47 +0000 | [diff] [blame] | 224 | { |
Eran Mitrani | 4c9440c | 2022-11-29 17:46:38 -0800 | [diff] [blame] | 225 | *size = ARRAY_SIZE(min_pci_sleep_states); |
| 226 | return min_pci_sleep_states; |
Tarun Tuli | c66ea98 | 2022-05-03 20:35:47 +0000 | [diff] [blame] | 227 | } |
| 228 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 229 | uint32_t soc_read_sci_irq_select(void) |
| 230 | { |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 231 | return read32p(soc_read_pmc_base() + IRQ_REG); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | static unsigned long soc_fill_dmar(unsigned long current) |
| 235 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 236 | const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 237 | const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 238 | |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 239 | if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 240 | const unsigned long tmp = current; |
| 241 | |
| 242 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 243 | current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 244 | |
| 245 | acpi_dmar_drhd_fixup(tmp, current); |
| 246 | } |
| 247 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 248 | const uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; |
| 249 | const bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; |
| 250 | |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 251 | if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 252 | const unsigned long tmp = current; |
| 253 | |
| 254 | current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 255 | current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 256 | |
| 257 | acpi_dmar_drhd_fixup(tmp, current); |
| 258 | } |
| 259 | |
John Zhao | 24ae31c | 2021-04-17 13:45:00 -0700 | [diff] [blame] | 260 | /* TCSS Thunderbolt root ports */ |
| 261 | for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 262 | if (is_devfn_enabled(SA_DEVFN_TBT(i))) { |
John Zhao | 24ae31c | 2021-04-17 13:45:00 -0700 | [diff] [blame] | 263 | const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; |
| 264 | const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; |
| 265 | if (tbtbar && tbten) { |
| 266 | const unsigned long tmp = current; |
| 267 | |
| 268 | current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 269 | current += acpi_create_dmar_ds_pci_br(current, 0, |
| 270 | SA_DEV_SLOT_TBT, i); |
John Zhao | 24ae31c | 2021-04-17 13:45:00 -0700 | [diff] [blame] | 271 | |
| 272 | acpi_dmar_drhd_fixup(tmp, current); |
| 273 | } |
| 274 | } |
| 275 | } |
| 276 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 277 | const uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; |
| 278 | const bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; |
| 279 | |
| 280 | if (vtvc0bar && vtvc0en) { |
| 281 | const unsigned long tmp = current; |
| 282 | |
| 283 | current += acpi_create_dmar_drhd(current, |
| 284 | DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
Arthur Heymans | d90154c | 2022-12-02 13:27:35 +0100 | [diff] [blame] | 285 | current += acpi_create_dmar_ds_ioapic_from_hw(current, |
| 286 | IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 287 | V_P2SB_CFG_IBDF_FUNC); |
| 288 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 289 | 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, |
| 290 | V_P2SB_CFG_HBDF_FUNC); |
| 291 | |
| 292 | acpi_dmar_drhd_fixup(tmp, current); |
| 293 | } |
| 294 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 295 | /* Add RMRR entry */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 296 | if (is_devfn_enabled(SA_DEVFN_IGD)) { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 297 | const unsigned long tmp = current; |
| 298 | current += acpi_create_dmar_rmrr(current, 0, |
| 299 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 300 | current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 301 | acpi_dmar_rmrr_fixup(tmp, current); |
| 302 | } |
| 303 | |
| 304 | return current; |
| 305 | } |
| 306 | |
| 307 | unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, |
| 308 | struct acpi_rsdp *rsdp) |
| 309 | { |
| 310 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 311 | |
| 312 | /* |
| 313 | * Create DMAR table only if we have VT-d capability and FSP does not override its |
| 314 | * feature. |
| 315 | */ |
| 316 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 317 | !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) |
| 318 | return current; |
| 319 | |
| 320 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 321 | acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); |
| 322 | current += dmar->header.length; |
| 323 | current = acpi_align_current(current); |
| 324 | acpi_add_table(rsdp, dmar); |
| 325 | |
| 326 | return current; |
| 327 | } |
| 328 | |
Kyösti Mälkki | c2b0a4f | 2020-06-28 22:39:59 +0300 | [diff] [blame] | 329 | void soc_fill_gnvs(struct global_nvs *gnvs) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 330 | { |
| 331 | config_t *config = config_of_soc(); |
| 332 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 333 | /* Enable DPTF based on mainboard configuration */ |
| 334 | gnvs->dpte = config->dptf_enable; |
| 335 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 336 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 337 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 338 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 339 | } |
| 340 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 341 | int soc_madt_sci_irq_polarity(int sci) |
| 342 | { |
| 343 | return MP_IRQ_POLARITY_HIGH; |
| 344 | } |