Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <delay.h> |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 6 | #include <reset.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 7 | #include <soc/addressmap.h> |
| 8 | #include <soc/clock.h> |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 9 | #include <soc/sdram.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 10 | #include <soc/grf.h> |
| 11 | #include <soc/soc.h> |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 12 | #include <timer.h> |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 13 | #include <types.h> |
| 14 | |
| 15 | #define DDR_PI_OFFSET 0x800 |
| 16 | #define DDR_PHY_OFFSET 0x2000 |
| 17 | #define DDRC0_PI_BASE_ADDR (DDRC0_BASE_ADDR + DDR_PI_OFFSET) |
| 18 | #define DDRC0_PHY_BASE_ADDR (DDRC0_BASE_ADDR + DDR_PHY_OFFSET) |
| 19 | #define DDRC1_PI_BASE_ADDR (DDRC1_BASE_ADDR + DDR_PI_OFFSET) |
| 20 | #define DDRC1_PHY_BASE_ADDR (DDRC1_BASE_ADDR + DDR_PHY_OFFSET) |
| 21 | |
| 22 | static struct rk3399_ddr_pctl_regs * const rk3399_ddr_pctl[2] = { |
| 23 | (void *)DDRC0_BASE_ADDR, (void *)DDRC1_BASE_ADDR }; |
| 24 | static struct rk3399_ddr_pi_regs * const rk3399_ddr_pi[2] = { |
| 25 | (void *)DDRC0_PI_BASE_ADDR, (void *)DDRC1_PI_BASE_ADDR }; |
| 26 | static struct rk3399_ddr_publ_regs * const rk3399_ddr_publ[2] = { |
| 27 | (void *)DDRC0_PHY_BASE_ADDR, (void *)DDRC1_PHY_BASE_ADDR }; |
| 28 | static struct rk3399_msch_regs * const rk3399_msch[2] = { |
| 29 | (void *)SERVER_MSCH0_BASE_ADDR, (void *)SERVER_MSCH1_BASE_ADDR }; |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 30 | static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE_ADDR; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * sys_reg bitfield struct |
| 34 | * [31] row_3_4_ch1 |
| 35 | * [30] row_3_4_ch0 |
| 36 | * [29:28] chinfo |
| 37 | * [27] rank_ch1 |
| 38 | * [26:25] col_ch1 |
| 39 | * [24] bk_ch1 |
| 40 | * [23:22] cs0_row_ch1 |
| 41 | * [21:20] cs1_row_ch1 |
| 42 | * [19:18] bw_ch1 |
| 43 | * [17:16] dbw_ch1; |
| 44 | * [15:13] ddrtype |
| 45 | * [12] channelnum |
| 46 | * [11] rank_ch0 |
| 47 | * [10:9] col_ch0 |
| 48 | * [8] bk_ch0 |
| 49 | * [7:6] cs0_row_ch0 |
| 50 | * [5:4] cs1_row_ch0 |
| 51 | * [3:2] bw_ch0 |
| 52 | * [1:0] dbw_ch0 |
| 53 | */ |
| 54 | #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) |
| 55 | #define SYS_REG_DEC_ROW_3_4(n, ch) ((n >> (30 + ch)) & 0x1) |
| 56 | #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) |
| 57 | #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) |
| 58 | #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) |
| 59 | #define SYS_REG_DEC_NUM_CH(n) (1 + ((n >> 12) & 0x1)) |
| 60 | #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) |
| 61 | #define SYS_REG_DEC_RANK(n, ch) (1 + ((n >> (11 + 16 * ch)) & 0x1)) |
| 62 | #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) |
| 63 | #define SYS_REG_DEC_COL(n, ch) (9 + ((n >> (9 + 16 * ch)) & 0x3)) |
| 64 | #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) \ |
| 65 | << (8 + ((ch) * 16))) |
| 66 | #define SYS_REG_DEC_BK(n, ch) (3 - ((n >> (8 + 16 * ch)) & 0x1)) |
| 67 | #define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16))) |
| 68 | #define SYS_REG_DEC_CS0_ROW(n, ch) (13 + ((n >> (6 + 16 * ch)) & 0x3)) |
| 69 | #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16))) |
| 70 | #define SYS_REG_DEC_CS1_ROW(n, ch) (13 + ((n >> (4 + 16 * ch)) & 0x3)) |
| 71 | #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) |
| 72 | #define SYS_REG_DEC_BW(n, ch) (2 >> ((n >> (2 + 16 * ch)) & 0x3)) |
| 73 | #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) |
| 74 | #define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) & 0x3)) |
| 75 | |
| 76 | #define DDR_STRIDE(n) write32(&rk3399_pmusgrf->soc_con4,\ |
| 77 | (0x1F << (10 + 16)) | (n << 10)) |
| 78 | |
| 79 | #define PRESET_SGRF_HOLD(n) ((0x1 << (6+16)) | ((n) << 6)) |
| 80 | #define PRESET_GPIO0_HOLD(n) ((0x1 << (7+16)) | ((n) << 7)) |
| 81 | #define PRESET_GPIO1_HOLD(n) ((0x1 << (8+16)) | ((n) << 8)) |
| 82 | |
| 83 | #define PHY_DRV_ODT_Hi_Z (0x0) |
| 84 | #define PHY_DRV_ODT_240 (0x1) |
| 85 | #define PHY_DRV_ODT_120 (0x8) |
| 86 | #define PHY_DRV_ODT_80 (0x9) |
| 87 | #define PHY_DRV_ODT_60 (0xc) |
| 88 | #define PHY_DRV_ODT_48 (0xd) |
| 89 | #define PHY_DRV_ODT_40 (0xe) |
| 90 | #define PHY_DRV_ODT_34_3 (0xf) |
| 91 | |
Moritz Fischer | 145ecc6 | 2021-02-17 21:39:08 -0800 | [diff] [blame] | 92 | #define MAX_RANKS_PER_CHANNEL 4 |
| 93 | |
Derek Basehore | 5282fe6 | 2016-06-17 23:29:18 -0700 | [diff] [blame] | 94 | static void copy_to_reg(u32 *dest, const u32 *src, u32 n) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 95 | { |
| 96 | int i; |
| 97 | |
| 98 | for (i = 0; i < n / sizeof(u32); i++) { |
| 99 | write32(dest, *src); |
| 100 | src++; |
| 101 | dest++; |
| 102 | } |
| 103 | } |
| 104 | |
Moritz Fischer | c73102d | 2021-02-18 14:43:20 -0800 | [diff] [blame] | 105 | static void phy_pctrl_reset(u32 channel) |
| 106 | { |
| 107 | rkclk_ddr_reset(channel, 1, 1); |
| 108 | udelay(10); |
| 109 | |
| 110 | rkclk_ddr_reset(channel, 1, 0); |
| 111 | udelay(10); |
| 112 | |
| 113 | rkclk_ddr_reset(channel, 0, 0); |
| 114 | udelay(10); |
| 115 | } |
| 116 | |
Moritz Fischer | 619c60f | 2021-02-19 17:56:10 -0800 | [diff] [blame] | 117 | static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, |
| 118 | u32 freq) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 119 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 120 | u32 *denali_phy = ddr_publ_regs->denali_phy; |
| 121 | |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 122 | if (freq <= 125*MHz) { |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 123 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 124 | setbits32(&denali_phy[86], (0x3 << 2) << 8); |
| 125 | setbits32(&denali_phy[214], (0x3 << 2) << 8); |
| 126 | setbits32(&denali_phy[342], (0x3 << 2) << 8); |
| 127 | setbits32(&denali_phy[470], (0x3 << 2) << 8); |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 128 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 129 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 130 | setbits32(&denali_phy[547], (0x3 << 2) << 16); |
| 131 | setbits32(&denali_phy[675], (0x3 << 2) << 16); |
| 132 | setbits32(&denali_phy[803], (0x3 << 2) << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 133 | } else { |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 134 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 135 | clrbits32(&denali_phy[86], (0x3 << 2) << 8); |
| 136 | clrbits32(&denali_phy[214], (0x3 << 2) << 8); |
| 137 | clrbits32(&denali_phy[342], (0x3 << 2) << 8); |
| 138 | clrbits32(&denali_phy[470], (0x3 << 2) << 8); |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 139 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 140 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 141 | clrbits32(&denali_phy[547], (0x3 << 2) << 16); |
| 142 | clrbits32(&denali_phy[675], (0x3 << 2) << 16); |
| 143 | clrbits32(&denali_phy[803], (0x3 << 2) << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 144 | } |
| 145 | } |
| 146 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 147 | static void set_memory_map(u32 channel, const struct rk3399_sdram_params *params) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 148 | { |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 149 | const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel]; |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 150 | u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; |
| 151 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 152 | u32 cs_map; |
| 153 | u32 reduc; |
Lin Huang | 60687b5 | 2016-10-17 10:31:30 +0800 | [diff] [blame] | 154 | u32 row; |
| 155 | |
| 156 | if ((sdram_ch->ddrconfig < 2) || (sdram_ch->ddrconfig == 4)) |
| 157 | row = 16; |
| 158 | else if (sdram_ch->ddrconfig == 3) |
| 159 | row = 14; |
| 160 | else |
| 161 | row = 15; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 162 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 163 | cs_map = (sdram_ch->rank > 1) ? 3 : 1; |
| 164 | reduc = (sdram_ch->bw == 2) ? 0 : 1; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 165 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 166 | clrsetbits32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); |
| 167 | clrsetbits32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), |
| 168 | ((3 - sdram_ch->bk) << 16) | |
| 169 | ((16 - row) << 24)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 170 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 171 | clrsetbits32(&denali_ctl[196], 0x3 | (1 << 16), |
| 172 | cs_map | (reduc << 16)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 173 | |
| 174 | /* PI_199 PI_COL_DIFF:RW:0:4 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 175 | clrsetbits32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 176 | |
| 177 | /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 178 | clrsetbits32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), |
| 179 | ((3 - sdram_ch->bk) << 16) | |
| 180 | ((16 - row) << 24)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 181 | /* PI_41 PI_CS_MAP:RW:24:4 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 182 | clrsetbits32(&denali_pi[41], 0xf << 24, cs_map << 24); |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 183 | if ((sdram_ch->rank == 1) && (params->dramtype == DDR3)) |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 184 | write32(&denali_pi[34], 0x2EC7FFFF); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 185 | } |
| 186 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 187 | static void set_ds_odt(u32 channel, const struct rk3399_sdram_params *params) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 188 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 189 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 190 | |
| 191 | u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 192 | u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 193 | u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 194 | u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 195 | u32 reg_value; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 196 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 197 | if (params->dramtype == LPDDR4) { |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 198 | tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 199 | tsel_rd_select_n = PHY_DRV_ODT_240; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 200 | |
| 201 | tsel_wr_select_p = PHY_DRV_ODT_40; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 202 | tsel_wr_select_n = PHY_DRV_ODT_40; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 203 | |
| 204 | tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 205 | tsel_idle_select_n = PHY_DRV_ODT_240; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 206 | |
| 207 | ca_tsel_wr_select_p = PHY_DRV_ODT_40; |
| 208 | ca_tsel_wr_select_n = PHY_DRV_ODT_40; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 209 | } else if (params->dramtype == LPDDR3) { |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 210 | tsel_rd_select_p = PHY_DRV_ODT_240; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 211 | tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 212 | |
| 213 | tsel_wr_select_p = PHY_DRV_ODT_34_3; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 214 | tsel_wr_select_n = PHY_DRV_ODT_34_3; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 215 | |
| 216 | tsel_idle_select_p = PHY_DRV_ODT_240; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 217 | tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 218 | |
| 219 | ca_tsel_wr_select_p = PHY_DRV_ODT_48; |
| 220 | ca_tsel_wr_select_n = PHY_DRV_ODT_48; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 221 | } else { |
| 222 | tsel_rd_select_p = PHY_DRV_ODT_240; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 223 | tsel_rd_select_n = PHY_DRV_ODT_240; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 224 | |
| 225 | tsel_wr_select_p = PHY_DRV_ODT_34_3; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 226 | tsel_wr_select_n = PHY_DRV_ODT_34_3; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 227 | |
| 228 | tsel_idle_select_p = PHY_DRV_ODT_240; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 229 | tsel_idle_select_n = PHY_DRV_ODT_240; |
Moritz Fischer | a76f659 | 2021-02-17 14:25:25 -0800 | [diff] [blame] | 230 | |
| 231 | ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; |
| 232 | ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 233 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 234 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 235 | if (params->odt == 1) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 236 | tsel_rd_en = 1; |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 237 | else |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 238 | tsel_rd_en = 0; |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 239 | |
| 240 | tsel_wr_en = 0; |
| 241 | tsel_idle_en = 0; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 242 | |
| 243 | /* |
| 244 | * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 |
| 245 | * sets termination values for read/idle cycles and drive strength |
| 246 | * for write cycles for DQ/DM |
| 247 | */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 248 | reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 249 | (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | |
| 250 | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 251 | clrsetbits32(&denali_phy[6], 0xffffff, reg_value); |
| 252 | clrsetbits32(&denali_phy[134], 0xffffff, reg_value); |
| 253 | clrsetbits32(&denali_phy[262], 0xffffff, reg_value); |
| 254 | clrsetbits32(&denali_phy[390], 0xffffff, reg_value); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 255 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 256 | /* |
| 257 | * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 |
| 258 | * sets termination values for read/idle cycles and drive strength |
| 259 | * for write cycles for DQS |
| 260 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 261 | clrsetbits32(&denali_phy[7], 0xffffff, reg_value); |
| 262 | clrsetbits32(&denali_phy[135], 0xffffff, reg_value); |
| 263 | clrsetbits32(&denali_phy[263], 0xffffff, reg_value); |
| 264 | clrsetbits32(&denali_phy[391], 0xffffff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 265 | |
| 266 | /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ |
Lin Huang | 9dc00ef | 2016-07-07 19:19:48 +0800 | [diff] [blame] | 267 | reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 268 | clrsetbits32(&denali_phy[544], 0xff, reg_value); |
| 269 | clrsetbits32(&denali_phy[672], 0xff, reg_value); |
| 270 | clrsetbits32(&denali_phy[800], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 271 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 272 | /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 273 | clrsetbits32(&denali_phy[928], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 274 | |
| 275 | /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 276 | clrsetbits32(&denali_phy[937], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 277 | |
| 278 | /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 279 | clrsetbits32(&denali_phy[935], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 280 | |
| 281 | /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 282 | clrsetbits32(&denali_phy[939], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 283 | |
| 284 | /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 285 | clrsetbits32(&denali_phy[929], 0xff, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 286 | |
| 287 | /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 288 | clrsetbits32(&denali_phy[924], 0xff, |
| 289 | tsel_wr_select_n | (tsel_wr_select_p << 4)); |
| 290 | clrsetbits32(&denali_phy[925], 0xff, |
| 291 | tsel_rd_select_n | (tsel_rd_select_p << 4)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 292 | |
| 293 | /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 294 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 295 | << 16; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 296 | clrsetbits32(&denali_phy[5], 0x7 << 16, reg_value); |
| 297 | clrsetbits32(&denali_phy[133], 0x7 << 16, reg_value); |
| 298 | clrsetbits32(&denali_phy[261], 0x7 << 16, reg_value); |
| 299 | clrsetbits32(&denali_phy[389], 0x7 << 16, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 300 | |
| 301 | /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 302 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 303 | << 24; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 304 | clrsetbits32(&denali_phy[6], 0x7 << 24, reg_value); |
| 305 | clrsetbits32(&denali_phy[134], 0x7 << 24, reg_value); |
| 306 | clrsetbits32(&denali_phy[262], 0x7 << 24, reg_value); |
| 307 | clrsetbits32(&denali_phy[390], 0x7 << 24, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 308 | |
| 309 | /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 310 | reg_value = tsel_wr_en << 8; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 311 | clrsetbits32(&denali_phy[518], 0x1 << 8, reg_value); |
| 312 | clrsetbits32(&denali_phy[646], 0x1 << 8, reg_value); |
| 313 | clrsetbits32(&denali_phy[774], 0x1 << 8, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 314 | |
| 315 | /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 316 | reg_value = tsel_wr_en << 17; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 317 | clrsetbits32(&denali_phy[933], 0x1 << 17, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 318 | /* |
| 319 | * pad_rst/cke/cs/clk_term tsel 1bits |
| 320 | * DENALI_PHY_938/936/940/934 offset_17 |
| 321 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 322 | clrsetbits32(&denali_phy[938], 0x1 << 17, reg_value); |
| 323 | clrsetbits32(&denali_phy[936], 0x1 << 17, reg_value); |
| 324 | clrsetbits32(&denali_phy[940], 0x1 << 17, reg_value); |
| 325 | clrsetbits32(&denali_phy[934], 0x1 << 17, reg_value); |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 326 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 327 | /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 328 | clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 329 | } |
| 330 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 331 | static void phy_io_config(u32 channel, const struct rk3399_sdram_params *params) |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 332 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 333 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 334 | u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 335 | u32 mode_sel = 0; |
Vadim Bendebury | ad6960c | 2016-06-17 17:14:18 -0700 | [diff] [blame] | 336 | u32 reg_value; |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 337 | u32 drv_value, odt_value; |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 338 | u32 speed; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 339 | |
| 340 | /* vref setting */ |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 341 | if (params->dramtype == LPDDR4) { |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 342 | /* LPDDR4 */ |
| 343 | vref_mode_dq = 0x6; |
| 344 | vref_value_dq = 0x1f; |
| 345 | vref_mode_ac = 0x6; |
| 346 | vref_value_ac = 0x1f; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 347 | } else if (params->dramtype == LPDDR3) { |
| 348 | if (params->odt == 1) { |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 349 | vref_mode_dq = 0x5; /* LPDDR3 ODT */ |
| 350 | drv_value = (read32(&denali_phy[6]) >> 12) & 0xf; |
| 351 | odt_value = (read32(&denali_phy[6]) >> 4) & 0xf; |
| 352 | if (drv_value == PHY_DRV_ODT_48) { |
| 353 | switch (odt_value) { |
| 354 | case PHY_DRV_ODT_240: |
| 355 | vref_value_dq = 0x16; |
| 356 | break; |
| 357 | case PHY_DRV_ODT_120: |
| 358 | vref_value_dq = 0x26; |
| 359 | break; |
| 360 | case PHY_DRV_ODT_60: |
| 361 | vref_value_dq = 0x36; |
| 362 | break; |
| 363 | default: |
| 364 | die("Halting: Invalid ODT value.\n"); |
| 365 | } |
| 366 | } else if (drv_value == PHY_DRV_ODT_40) { |
| 367 | switch (odt_value) { |
| 368 | case PHY_DRV_ODT_240: |
| 369 | vref_value_dq = 0x19; |
| 370 | break; |
| 371 | case PHY_DRV_ODT_120: |
| 372 | vref_value_dq = 0x23; |
| 373 | break; |
| 374 | case PHY_DRV_ODT_60: |
| 375 | vref_value_dq = 0x31; |
| 376 | break; |
| 377 | default: |
| 378 | die("Halting: Invalid ODT value.\n"); |
| 379 | } |
| 380 | } else if (drv_value == PHY_DRV_ODT_34_3) { |
| 381 | switch (odt_value) { |
| 382 | case PHY_DRV_ODT_240: |
| 383 | vref_value_dq = 0x17; |
| 384 | break; |
| 385 | case PHY_DRV_ODT_120: |
| 386 | vref_value_dq = 0x20; |
| 387 | break; |
| 388 | case PHY_DRV_ODT_60: |
| 389 | vref_value_dq = 0x2e; |
| 390 | break; |
| 391 | default: |
| 392 | die("Halting: Invalid ODT value.\n"); |
| 393 | } |
| 394 | } else { |
| 395 | die("Halting: Invalid DRV value.\n"); |
| 396 | } |
| 397 | } else { |
| 398 | vref_mode_dq = 0x2; /* LPDDR3 */ |
| 399 | vref_value_dq = 0x1f; |
| 400 | } |
| 401 | vref_mode_ac = 0x2; |
| 402 | vref_value_ac = 0x1f; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 403 | } else if (params->dramtype == DDR3) { |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 404 | /* DDR3L */ |
| 405 | vref_mode_dq = 0x1; |
| 406 | vref_value_dq = 0x1f; |
| 407 | vref_mode_ac = 0x1; |
| 408 | vref_value_ac = 0x1f; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 409 | } else { |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 410 | die("Halting: Unknown DRAM type.\n"); |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 411 | } |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 412 | |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 413 | reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; |
| 414 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 415 | /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 416 | clrsetbits32(&denali_phy[913], 0xfff << 8, reg_value << 8); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 417 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 418 | clrsetbits32(&denali_phy[914], 0xfff, reg_value); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 419 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 420 | clrsetbits32(&denali_phy[914], 0xfff << 16, reg_value << 16); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 421 | /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 422 | clrsetbits32(&denali_phy[915], 0xfff, reg_value); |
Lin Huang | df5ead9 | 2016-07-07 19:29:55 +0800 | [diff] [blame] | 423 | |
| 424 | reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; |
| 425 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 426 | /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 427 | clrsetbits32(&denali_phy[915], 0xfff << 16, reg_value << 16); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 428 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 429 | if (params->dramtype == LPDDR4) |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 430 | mode_sel = 0x6; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 431 | else if (params->dramtype == LPDDR3) |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 432 | mode_sel = 0x0; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 433 | else if (params->dramtype == DDR3) |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 434 | mode_sel = 0x1; |
| 435 | |
| 436 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 437 | clrsetbits32(&denali_phy[924], 0x7 << 15, mode_sel << 15); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 438 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 439 | clrsetbits32(&denali_phy[926], 0x7 << 6, mode_sel << 6); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 440 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 441 | clrsetbits32(&denali_phy[927], 0x7 << 6, mode_sel << 6); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 442 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 443 | clrsetbits32(&denali_phy[928], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 444 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 445 | clrsetbits32(&denali_phy[929], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 446 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 447 | clrsetbits32(&denali_phy[935], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 448 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 449 | clrsetbits32(&denali_phy[937], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 450 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 451 | clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 452 | |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 453 | /* speed setting */ |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 454 | if (params->ddr_freq < 400 * MHz) |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 455 | speed = 0x0; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 456 | else if (params->ddr_freq < 800 * MHz) |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 457 | speed = 0x1; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 458 | else if (params->ddr_freq < 1200 * MHz) |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 459 | speed = 0x2; |
| 460 | else |
| 461 | speed = 0x3; |
| 462 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 463 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 464 | clrsetbits32(&denali_phy[924], 0x3 << 21, speed << 21); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 465 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 466 | clrsetbits32(&denali_phy[926], 0x3 << 9, speed << 9); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 467 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 468 | clrsetbits32(&denali_phy[927], 0x3 << 9, speed << 9); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 469 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 470 | clrsetbits32(&denali_phy[928], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 471 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 472 | clrsetbits32(&denali_phy[929], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 473 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 474 | clrsetbits32(&denali_phy[935], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 475 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 476 | clrsetbits32(&denali_phy[937], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 477 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 478 | clrsetbits32(&denali_phy[939], 0x3 << 17, speed << 17); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 479 | } |
| 480 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 481 | static int pctl_cfg(u32 channel, const struct rk3399_sdram_params *params) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 482 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 483 | u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; |
| 484 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
| 485 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 486 | const u32 *params_ctl = params->pctl_regs.denali_ctl; |
| 487 | const u32 *params_phy = params->phy_regs.denali_phy; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 488 | u32 tmp, tmp1, tmp2; |
| 489 | u32 pwrup_srefresh_exit; |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 490 | struct stopwatch sw; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 491 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 492 | /* |
| 493 | * work around controller bug: |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 494 | * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed |
| 495 | */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 496 | copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], |
| 497 | sizeof(struct rk3399_ddr_pctl_regs) - 4); |
| 498 | write32(&denali_ctl[0], params_ctl[0]); |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 499 | copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 500 | sizeof(struct rk3399_ddr_pi_regs)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 501 | /* rank count need to set for init */ |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 502 | set_memory_map(channel, params); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 503 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 504 | write32(&denali_phy[910], params->phy_regs.denali_phy[910]); |
| 505 | write32(&denali_phy[911], params->phy_regs.denali_phy[911]); |
| 506 | write32(&denali_phy[912], params->phy_regs.denali_phy[912]); |
Lin Huang | e757bf9 | 2016-09-21 18:19:24 +0800 | [diff] [blame] | 507 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 508 | pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 509 | clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 510 | |
| 511 | /* PHY_DLL_RST_EN */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 512 | clrsetbits32(&denali_phy[957], 0x3 << 24, 1 << 24); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 513 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 514 | setbits32(&denali_pi[0], START); |
| 515 | setbits32(&denali_ctl[0], START); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 516 | |
| 517 | while (1) { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 518 | tmp = read32(&denali_phy[920]); |
| 519 | tmp1 = read32(&denali_phy[921]); |
| 520 | tmp2 = read32(&denali_phy[922]); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 521 | if ((((tmp >> 16) & 0x1) == 0x1) && |
| 522 | (((tmp1 >> 16) & 0x1) == 0x1) && |
| 523 | (((tmp1 >> 0) & 0x1) == 0x1) && |
| 524 | (((tmp2 >> 0) & 0x1) == 0x1)) |
| 525 | break; |
| 526 | } |
| 527 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 528 | copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); |
| 529 | copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); |
| 530 | copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4); |
| 531 | copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4); |
| 532 | copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4); |
| 533 | copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); |
| 534 | copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); |
| 535 | copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 536 | set_ds_odt(channel, params); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 537 | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 538 | /* |
| 539 | * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 |
| 540 | * dqs_tsel_wr_end[7:4] add Half cycle |
| 541 | */ |
| 542 | tmp = (read32(&denali_phy[84]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 543 | clrsetbits32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 544 | tmp = (read32(&denali_phy[212]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 545 | clrsetbits32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 546 | tmp = (read32(&denali_phy[340]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 547 | clrsetbits32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 548 | tmp = (read32(&denali_phy[468]) >> 8) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 549 | clrsetbits32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 550 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 551 | /* |
| 552 | * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 |
| 553 | * dq_tsel_wr_end[7:4] add Half cycle |
| 554 | */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 555 | tmp = (read32(&denali_phy[83]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 556 | clrsetbits32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 557 | tmp = (read32(&denali_phy[211]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 558 | clrsetbits32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 559 | tmp = (read32(&denali_phy[339]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 560 | clrsetbits32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 561 | tmp = (read32(&denali_phy[467]) >> 16) & 0xff; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 562 | clrsetbits32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 563 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 564 | phy_io_config(channel, params); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 565 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 566 | /* PHY_DLL_RST_EN */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 567 | clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 568 | |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 569 | /* FIXME: need to care ERROR bit */ |
| 570 | stopwatch_init_msecs_expire(&sw, 100); |
| 571 | while (!(read32(&denali_ctl[203]) & (1 << 3))) { |
| 572 | if (stopwatch_expired(&sw)) |
| 573 | return -1; |
| 574 | } |
| 575 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 576 | clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, |
| 577 | pwrup_srefresh_exit); |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 578 | return 0; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 579 | } |
| 580 | |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 581 | static void select_per_cs_training_index(u32 channel, u32 rank) |
| 582 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 583 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 584 | |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 585 | /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 586 | if ((read32(&denali_phy[84])>>16) & 1) { |
Derek Basehore | 9e624fc | 2016-06-22 16:42:30 -0700 | [diff] [blame] | 587 | /* |
| 588 | * PHY_8/136/264/392 |
| 589 | * phy_per_cs_training_index_X 1bit offset_24 |
| 590 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 591 | clrsetbits32(&denali_phy[8], 0x1 << 24, rank << 24); |
| 592 | clrsetbits32(&denali_phy[136], 0x1 << 24, rank << 24); |
| 593 | clrsetbits32(&denali_phy[264], 0x1 << 24, rank << 24); |
| 594 | clrsetbits32(&denali_phy[392], 0x1 << 24, rank << 24); |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 595 | } |
| 596 | } |
| 597 | |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 598 | static void override_write_leveling_value(u32 channel) |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 599 | { |
Jianqun Xu | 681b6b9 | 2016-09-11 18:26:42 +0800 | [diff] [blame] | 600 | u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 601 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 602 | u32 byte; |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 603 | |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 604 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 605 | setbits32(&denali_phy[896], 1); |
Jianqun Xu | 681b6b9 | 2016-09-11 18:26:42 +0800 | [diff] [blame] | 606 | |
| 607 | /* |
| 608 | * PHY_8/136/264/392 |
| 609 | * phy_per_cs_training_multicast_en_X 1bit offset_16 |
| 610 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 611 | clrsetbits32(&denali_phy[8], 0x1 << 16, 1 << 16); |
| 612 | clrsetbits32(&denali_phy[136], 0x1 << 16, 1 << 16); |
| 613 | clrsetbits32(&denali_phy[264], 0x1 << 16, 1 << 16); |
| 614 | clrsetbits32(&denali_phy[392], 0x1 << 16, 1 << 16); |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 615 | |
| 616 | for (byte = 0; byte < 4; byte++) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 617 | clrsetbits32(&denali_phy[63 + (128 * byte)], 0xffff << 16, |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 618 | 0x200 << 16); |
| 619 | |
| 620 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 621 | clrbits32(&denali_phy[896], 1); |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 622 | |
| 623 | /* CTL_200 ctrlupd_req 1bit offset_8 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 624 | clrsetbits32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 625 | } |
| 626 | |
Moritz Fischer | 145ecc6 | 2021-02-17 21:39:08 -0800 | [diff] [blame] | 627 | static u32 get_rank_mask(u32 channel, const struct rk3399_sdram_params *params) |
| 628 | { |
| 629 | const u32 rank = params->ch[channel].rank; |
| 630 | |
| 631 | /* required rank mask is different for LPDDR4 */ |
| 632 | if (params->dramtype == LPDDR4) |
| 633 | return (rank == 1) ? 0x5 : 0xf; |
| 634 | else |
| 635 | return (rank == 1) ? 0x1 : 0x3; |
| 636 | } |
| 637 | |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 638 | static int data_training_ca(u32 channel, const struct rk3399_sdram_params *params) |
| 639 | { |
| 640 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
| 641 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 642 | u32 obs_0, obs_1, obs_2; |
Moritz Fischer | 145ecc6 | 2021-02-17 21:39:08 -0800 | [diff] [blame] | 643 | const u32 rank_mask = get_rank_mask(channel, params); |
| 644 | u32 i, tmp; |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 645 | |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 646 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 647 | write32(&denali_pi[175], 0x00003f7c); |
| 648 | |
Moritz Fischer | 145ecc6 | 2021-02-17 21:39:08 -0800 | [diff] [blame] | 649 | for (i = 0; i < MAX_RANKS_PER_CHANNEL; i++) { |
| 650 | if (!(rank_mask & (1 << i))) |
| 651 | continue; |
| 652 | |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 653 | select_per_cs_training_index(channel, i); |
| 654 | /* PI_100 PI_CALVL_EN:RW:8:2 */ |
| 655 | clrsetbits32(&denali_pi[100], 0x3 << 8, 0x2 << 8); |
| 656 | /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ |
| 657 | clrsetbits32(&denali_pi[92], (0x1 << 16) | (0x3 << 24), |
| 658 | (0x1 << 16) | (i << 24)); |
| 659 | |
| 660 | while (1) { |
| 661 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 662 | tmp = read32(&denali_pi[174]) >> 8; |
| 663 | |
| 664 | /* |
| 665 | * check status obs |
| 666 | * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 |
| 667 | */ |
| 668 | obs_0 = read32(&denali_phy[532]); |
| 669 | obs_1 = read32(&denali_phy[660]); |
| 670 | obs_2 = read32(&denali_phy[788]); |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 671 | if (((obs_0 >> 30) & 0x3) || |
| 672 | ((obs_1 >> 30) & 0x3) || |
| 673 | ((obs_2 >> 30) & 0x3)) |
| 674 | return -1; |
| 675 | if ((((tmp >> 11) & 0x1) == 0x1) && |
| 676 | (((tmp >> 13) & 0x1) == 0x1) && |
| 677 | (((tmp >> 5) & 0x1) == 0x0)) |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 678 | break; |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 679 | else if (((tmp >> 5) & 0x1) == 0x1) |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 680 | return -1; |
| 681 | } |
| 682 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 683 | write32(&denali_pi[175], 0x00003f7c); |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 684 | } |
| 685 | clrbits32(&denali_pi[100], 0x3 << 8); |
| 686 | |
| 687 | return 0; |
| 688 | } |
| 689 | |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 690 | static int data_training_wl(u32 channel, const struct rk3399_sdram_params *params) |
| 691 | { |
| 692 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
| 693 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 694 | u32 obs_0, obs_1, obs_2, obs_3; |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 695 | u32 rank = params->ch[channel].rank; |
| 696 | u32 i, tmp; |
| 697 | |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 698 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 699 | write32(&denali_pi[175], 0x00003f7c); |
| 700 | |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 701 | for (i = 0; i < rank; i++) { |
| 702 | select_per_cs_training_index(channel, i); |
| 703 | /* PI_60 PI_WRLVL_EN:RW:8:2 */ |
| 704 | clrsetbits32(&denali_pi[60], 0x3 << 8, 0x2 << 8); |
| 705 | /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ |
| 706 | clrsetbits32(&denali_pi[59], (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); |
| 707 | |
| 708 | while (1) { |
| 709 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 710 | tmp = read32(&denali_pi[174]) >> 8; |
| 711 | |
| 712 | /* |
| 713 | * check status obs, if error maybe can not |
| 714 | * get leveling done PHY_40/168/296/424 |
| 715 | * phy_wrlvl_status_obs_X:0:13 |
| 716 | */ |
| 717 | obs_0 = read32(&denali_phy[40]); |
| 718 | obs_1 = read32(&denali_phy[168]); |
| 719 | obs_2 = read32(&denali_phy[296]); |
| 720 | obs_3 = read32(&denali_phy[424]); |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 721 | if (((obs_0 >> 12) & 0x1) || |
| 722 | ((obs_1 >> 12) & 0x1) || |
| 723 | ((obs_2 >> 12) & 0x1) || |
| 724 | ((obs_3 >> 12) & 0x1)) |
| 725 | return -1; |
| 726 | if ((((tmp >> 10) & 0x1) == 0x1) && |
| 727 | (((tmp >> 13) & 0x1) == 0x1) && |
| 728 | (((tmp >> 4) & 0x1) == 0x0)) |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 729 | break; |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 730 | else if (((tmp >> 4) & 0x1) == 0x1) |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 731 | return -1; |
| 732 | } |
| 733 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 734 | write32(&denali_pi[175], 0x00003f7c); |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | override_write_leveling_value(channel); |
| 738 | clrbits32(&denali_pi[60], 0x3 << 8); |
| 739 | |
| 740 | return 0; |
| 741 | } |
| 742 | |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 743 | static int data_training_rg(u32 channel, const struct rk3399_sdram_params *params) |
| 744 | { |
| 745 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
| 746 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
| 747 | u32 rank = params->ch[channel].rank; |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 748 | u32 obs_0, obs_1, obs_2, obs_3; |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 749 | u32 reg_value = 0; |
| 750 | u32 i, tmp; |
| 751 | |
| 752 | /* |
| 753 | * The differential signal of DQS needs to keep low level |
| 754 | * before gate training. RPULL will connect 4Kn from PADP |
| 755 | * to VSS and a 4Kn from PADN to VDDQ to ensure it. |
| 756 | * But if it has PHY side ODT connect at this time, |
| 757 | * it will change the DQS signal level. So disable PHY |
| 758 | * side ODT before gate training and restore ODT state |
| 759 | * after gate training. |
| 760 | */ |
| 761 | if (params->dramtype != LPDDR4) { |
| 762 | reg_value = (read32(&denali_phy[6]) >> 24) & 0x7; |
| 763 | |
| 764 | /* |
| 765 | * phy_dqs_tsel_enable_X 3bits |
| 766 | * DENALI_PHY_6/134/262/390 offset_24 |
| 767 | */ |
| 768 | clrbits32(&denali_phy[6], 0x7 << 24); |
| 769 | clrbits32(&denali_phy[134], 0x7 << 24); |
| 770 | clrbits32(&denali_phy[262], 0x7 << 24); |
| 771 | clrbits32(&denali_phy[390], 0x7 << 24); |
| 772 | } |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 773 | |
| 774 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 775 | write32(&denali_pi[175], 0x00003f7c); |
| 776 | |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 777 | for (i = 0; i < rank; i++) { |
| 778 | select_per_cs_training_index(channel, i); |
| 779 | /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ |
| 780 | clrsetbits32(&denali_pi[80], 0x3 << 24, 0x2 << 24); |
| 781 | /* |
| 782 | * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 |
| 783 | * PI_RDLVL_CS:RW:24:2 |
| 784 | */ |
| 785 | clrsetbits32(&denali_pi[74], (0x1 << 16) | (0x3 << 24), |
| 786 | (0x1 << 16) | (i << 24)); |
| 787 | |
| 788 | while (1) { |
| 789 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 790 | tmp = read32(&denali_pi[174]) >> 8; |
| 791 | |
| 792 | /* |
| 793 | * check status obs |
| 794 | * PHY_43/171/299/427 |
| 795 | * PHY_GTLVL_STATUS_OBS_x:16:8 |
| 796 | */ |
| 797 | obs_0 = read32(&denali_phy[43]); |
| 798 | obs_1 = read32(&denali_phy[171]); |
| 799 | obs_2 = read32(&denali_phy[299]); |
| 800 | obs_3 = read32(&denali_phy[427]); |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 801 | if (((obs_0 >> (16 + 6)) & 0x3) || |
| 802 | ((obs_1 >> (16 + 6)) & 0x3) || |
| 803 | ((obs_2 >> (16 + 6)) & 0x3) || |
| 804 | ((obs_3 >> (16 + 6)) & 0x3)) |
| 805 | return -1; |
| 806 | if ((((tmp >> 9) & 0x1) == 0x1) && |
| 807 | (((tmp >> 13) & 0x1) == 0x1) && |
| 808 | (((tmp >> 3) & 0x1) == 0x0)) |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 809 | break; |
Julius Werner | 7f0d3de | 2021-02-24 16:41:55 -0800 | [diff] [blame] | 810 | else if (((tmp >> 3) & 0x1) == 0x1) |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 811 | return -1; |
| 812 | } |
| 813 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 814 | write32(&denali_pi[175], 0x00003f7c); |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 815 | } |
| 816 | clrbits32(&denali_pi[80], 0x3 << 24); |
| 817 | |
| 818 | if (params->dramtype != LPDDR4) { |
| 819 | /* |
| 820 | * phy_dqs_tsel_enable_X 3bits |
| 821 | * DENALI_PHY_6/134/262/390 offset_24 |
| 822 | */ |
| 823 | tmp = reg_value << 24; |
| 824 | clrsetbits32(&denali_phy[6], 0x7 << 24, tmp); |
| 825 | clrsetbits32(&denali_phy[134], 0x7 << 24, tmp); |
| 826 | clrsetbits32(&denali_phy[262], 0x7 << 24, tmp); |
| 827 | clrsetbits32(&denali_phy[390], 0x7 << 24, tmp); |
| 828 | } |
| 829 | return 0; |
| 830 | } |
| 831 | |
Moritz Fischer | 401c7a6 | 2021-02-17 13:57:36 -0800 | [diff] [blame] | 832 | static int data_training_rl(u32 channel, const struct rk3399_sdram_params *params) |
| 833 | { |
| 834 | u32 rank = params->ch[channel].rank; |
| 835 | u32 i, tmp; |
| 836 | |
| 837 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
| 838 | |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 839 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 840 | write32(&denali_pi[175], 0x00003f7c); |
| 841 | |
Moritz Fischer | 401c7a6 | 2021-02-17 13:57:36 -0800 | [diff] [blame] | 842 | for (i = 0; i < rank; i++) { |
| 843 | select_per_cs_training_index(channel, i); |
| 844 | /* PI_80 PI_RDLVL_EN:RW:16:2 */ |
| 845 | clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16); |
| 846 | /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ |
| 847 | clrsetbits32(&denali_pi[74], (0x1 << 8) | (0x3 << 24), (0x1 << 8) | (i << 24)); |
| 848 | |
| 849 | while (1) { |
| 850 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 851 | tmp = read32(&denali_pi[174]) >> 8; |
| 852 | |
| 853 | /* |
| 854 | * make sure status obs not report error bit |
| 855 | * PHY_46/174/302/430 |
| 856 | * phy_rdlvl_status_obs_X:16:8 |
| 857 | */ |
| 858 | if ((((tmp >> 8) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) |
| 859 | && (((tmp >> 2) & 0x1) == 0x0)) |
| 860 | break; |
| 861 | else if (((tmp >> 2) & 0x1) == 0x1) |
| 862 | return -1; |
| 863 | } |
| 864 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 865 | write32(&denali_pi[175], 0x00003f7c); |
Moritz Fischer | 401c7a6 | 2021-02-17 13:57:36 -0800 | [diff] [blame] | 866 | } |
| 867 | clrbits32(&denali_pi[80], 0x3 << 16); |
| 868 | |
| 869 | return 0; |
| 870 | } |
| 871 | |
Moritz Fischer | c867cd3 | 2021-02-17 14:01:44 -0800 | [diff] [blame] | 872 | static int data_training_wdql(u32 channel, const struct rk3399_sdram_params *params) |
| 873 | { |
| 874 | u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; |
Moritz Fischer | d4f81bc | 2021-02-17 21:42:41 -0800 | [diff] [blame] | 875 | const u32 rank_mask = get_rank_mask(channel, params); |
Moritz Fischer | c867cd3 | 2021-02-17 14:01:44 -0800 | [diff] [blame] | 876 | u32 i, tmp; |
| 877 | |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 878 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 879 | write32(&denali_pi[175], 0x00003f7c); |
| 880 | |
Moritz Fischer | d4f81bc | 2021-02-17 21:42:41 -0800 | [diff] [blame] | 881 | for (i = 0; i < MAX_RANKS_PER_CHANNEL; i++) { |
| 882 | if (!(rank_mask & (1 << i))) |
| 883 | continue; |
| 884 | |
Moritz Fischer | c867cd3 | 2021-02-17 14:01:44 -0800 | [diff] [blame] | 885 | select_per_cs_training_index(channel, i); |
| 886 | /* |
| 887 | * disable PI_WDQLVL_VREF_EN before wdq leveling? |
| 888 | * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 |
| 889 | */ |
| 890 | clrbits32(&denali_pi[181], 0x1 << 8); |
| 891 | /* PI_124 PI_WDQLVL_EN:RW:16:2 */ |
| 892 | clrsetbits32(&denali_pi[124], 0x3 << 16, 0x2 << 16); |
| 893 | /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ |
| 894 | clrsetbits32(&denali_pi[121], (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); |
| 895 | |
| 896 | while (1) { |
| 897 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 898 | tmp = read32(&denali_pi[174]) >> 8; |
| 899 | if ((((tmp >> 12) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) |
| 900 | && (((tmp >> 6) & 0x1) == 0x0)) |
| 901 | break; |
| 902 | else if (((tmp >> 6) & 0x1) == 0x1) |
| 903 | return -1; |
| 904 | } |
| 905 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
Moritz Fischer | d8f352b | 2021-02-17 21:34:53 -0800 | [diff] [blame] | 906 | write32(&denali_pi[175], 0x00003f7c); |
Moritz Fischer | c867cd3 | 2021-02-17 14:01:44 -0800 | [diff] [blame] | 907 | } |
| 908 | clrbits32(&denali_pi[124], 0x3 << 16); |
| 909 | |
| 910 | return 0; |
| 911 | } |
| 912 | |
| 913 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 914 | static int data_training(u32 channel, const struct rk3399_sdram_params *params, |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 915 | u32 training_flag) |
| 916 | { |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 917 | u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 918 | int ret; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 919 | |
| 920 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 921 | setbits32(&denali_phy[927], (1 << 22)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 922 | |
Patrick Georgi | e640716 | 2016-11-02 11:36:07 +0100 | [diff] [blame] | 923 | if (training_flag == PI_FULL_TRAINING) { |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 924 | if (params->dramtype == LPDDR4) { |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 925 | training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | |
| 926 | PI_READ_GATE_TRAINING | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 927 | PI_READ_LEVELING | PI_WDQ_LEVELING; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 928 | } else if (params->dramtype == LPDDR3) { |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 929 | training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | |
Lin Huang | f435f92 | 2016-10-09 09:37:10 +0800 | [diff] [blame] | 930 | PI_READ_GATE_TRAINING; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 931 | } else if (params->dramtype == DDR3) { |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 932 | training_flag = PI_WRITE_LEVELING | |
Derek Basehore | f3b3ccf | 2016-06-23 14:28:12 -0700 | [diff] [blame] | 933 | PI_READ_GATE_TRAINING | |
| 934 | PI_READ_LEVELING; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 935 | } |
| 936 | } |
| 937 | |
Lin Huang | 321a6a9 | 2016-06-16 10:34:04 +0800 | [diff] [blame] | 938 | /* ca training(LPDDR4,LPDDR3 support) */ |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 939 | if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 940 | ret = data_training_ca(channel, params); |
| 941 | if (ret) { |
Moritz Fischer | abefcc2 | 2021-02-28 18:30:11 -0800 | [diff] [blame] | 942 | printk(BIOS_ERR, "Channel %d CA training failed\n", channel); |
Moritz Fischer | f71902d | 2021-02-17 13:35:15 -0800 | [diff] [blame] | 943 | return ret; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 944 | } |
| 945 | } |
| 946 | |
| 947 | /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ |
| 948 | if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 949 | ret = data_training_wl(channel, params); |
| 950 | if (ret) { |
Moritz Fischer | abefcc2 | 2021-02-28 18:30:11 -0800 | [diff] [blame] | 951 | printk(BIOS_ERR, "Channel %d WL training failed\n", channel); |
Moritz Fischer | 68365e1 | 2021-02-17 13:39:01 -0800 | [diff] [blame] | 952 | return ret; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 953 | } |
| 954 | } |
| 955 | |
| 956 | /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ |
| 957 | if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 958 | ret = data_training_rg(channel, params); |
| 959 | if (ret) { |
Moritz Fischer | abefcc2 | 2021-02-28 18:30:11 -0800 | [diff] [blame] | 960 | printk(BIOS_ERR, "Channel %d RG training failed\n", channel); |
Moritz Fischer | 12d3600 | 2021-02-17 13:47:42 -0800 | [diff] [blame] | 961 | return ret; |
Lin Huang | aaf6322 | 2017-02-22 18:22:19 +0800 | [diff] [blame] | 962 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 963 | } |
| 964 | |
| 965 | /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ |
| 966 | if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { |
Moritz Fischer | 401c7a6 | 2021-02-17 13:57:36 -0800 | [diff] [blame] | 967 | ret = data_training_rl(channel, params); |
| 968 | if (ret) { |
Moritz Fischer | abefcc2 | 2021-02-28 18:30:11 -0800 | [diff] [blame] | 969 | printk(BIOS_ERR, "Channel %d RL training failed\n", channel); |
Moritz Fischer | 401c7a6 | 2021-02-17 13:57:36 -0800 | [diff] [blame] | 970 | return ret; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 971 | } |
| 972 | } |
| 973 | |
| 974 | /* wdq leveling(LPDDR4 support) */ |
| 975 | if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { |
Moritz Fischer | c867cd3 | 2021-02-17 14:01:44 -0800 | [diff] [blame] | 976 | ret = data_training_wdql(channel, params); |
| 977 | if (ret) { |
Moritz Fischer | abefcc2 | 2021-02-28 18:30:11 -0800 | [diff] [blame] | 978 | printk(BIOS_ERR, "Channel %d WDQL training failed\n", channel); |
Moritz Fischer | c867cd3 | 2021-02-17 14:01:44 -0800 | [diff] [blame] | 979 | return ret; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 980 | } |
| 981 | } |
| 982 | |
| 983 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 984 | clrbits32(&denali_phy[927], (1 << 22)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 985 | |
| 986 | return 0; |
| 987 | } |
| 988 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 989 | static void set_ddrconfig(const struct rk3399_sdram_params *params, |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 990 | unsigned char channel, u32 ddrconfig) |
| 991 | { |
| 992 | /* only need to set ddrconfig */ |
| 993 | struct rk3399_msch_regs *ddr_msch_regs = rk3399_msch[channel]; |
| 994 | unsigned int cs0_cap = 0; |
| 995 | unsigned int cs1_cap = 0; |
| 996 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 997 | cs0_cap = (1 << (params->ch[channel].cs0_row |
| 998 | + params->ch[channel].col |
| 999 | + params->ch[channel].bk |
| 1000 | + params->ch[channel].bw - 20)); |
| 1001 | if (params->ch[channel].rank > 1) |
| 1002 | cs1_cap = cs0_cap >> (params->ch[channel].cs0_row |
| 1003 | - params->ch[channel].cs1_row); |
| 1004 | if (params->ch[channel].row_3_4) { |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1005 | cs0_cap = cs0_cap * 3 / 4; |
| 1006 | cs1_cap = cs1_cap * 3 / 4; |
| 1007 | } |
| 1008 | |
Lin Huang | 60687b5 | 2016-10-17 10:31:30 +0800 | [diff] [blame] | 1009 | write32(&ddr_msch_regs->ddrconf, ddrconfig | (ddrconfig << 8)); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1010 | write32(&ddr_msch_regs->ddrsize, ((cs0_cap / 32) & 0xff) | |
| 1011 | (((cs1_cap / 32) & 0xff) << 8)); |
| 1012 | } |
| 1013 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1014 | static void dram_all_config(const struct rk3399_sdram_params *params) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1015 | { |
| 1016 | u32 sys_reg = 0; |
| 1017 | unsigned int channel; |
| 1018 | unsigned int use; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1019 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1020 | sys_reg |= SYS_REG_ENC_DDRTYPE(params->dramtype); |
| 1021 | sys_reg |= SYS_REG_ENC_NUM_CH(params->num_channels); |
| 1022 | for (channel = 0, use = 0; (use < params->num_channels) && (channel < 2); channel++) { |
| 1023 | const struct rk3399_sdram_channel *info = ¶ms->ch[channel]; |
Derek Basehore | 1dd0bc0 | 2016-06-23 14:35:22 -0700 | [diff] [blame] | 1024 | struct rk3399_msch_regs *ddr_msch_regs; |
| 1025 | const struct rk3399_msch_timings *noc_timing; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1026 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1027 | if (params->ch[channel].col == 0) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1028 | continue; |
| 1029 | use++; |
| 1030 | sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel); |
| 1031 | sys_reg |= SYS_REG_ENC_CHINFO(channel); |
| 1032 | sys_reg |= SYS_REG_ENC_RANK(info->rank, channel); |
| 1033 | sys_reg |= SYS_REG_ENC_COL(info->col, channel); |
| 1034 | sys_reg |= SYS_REG_ENC_BK(info->bk, channel); |
| 1035 | sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel); |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1036 | if (params->ch[channel].rank > 1) |
Lin Huang | 4b9cd53 | 2016-05-05 18:38:59 +0800 | [diff] [blame] | 1037 | sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1038 | sys_reg |= SYS_REG_ENC_BW(info->bw, channel); |
| 1039 | sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel); |
| 1040 | |
Derek Basehore | 1dd0bc0 | 2016-06-23 14:35:22 -0700 | [diff] [blame] | 1041 | ddr_msch_regs = rk3399_msch[channel]; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1042 | noc_timing = ¶ms->ch[channel].noc_timings; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1043 | write32(&ddr_msch_regs->ddrtiminga0.d32, |
| 1044 | noc_timing->ddrtiminga0.d32); |
| 1045 | write32(&ddr_msch_regs->ddrtimingb0.d32, |
| 1046 | noc_timing->ddrtimingb0.d32); |
| 1047 | write32(&ddr_msch_regs->ddrtimingc0.d32, |
| 1048 | noc_timing->ddrtimingc0.d32); |
| 1049 | write32(&ddr_msch_regs->devtodev0.d32, |
| 1050 | noc_timing->devtodev0.d32); |
| 1051 | write32(&ddr_msch_regs->ddrmode.d32, |
| 1052 | noc_timing->ddrmode.d32); |
| 1053 | |
| 1054 | /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1055 | if (params->ch[channel].rank == 1) |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 1056 | setbits32(&rk3399_ddr_pctl[channel]->denali_ctl[276], |
| 1057 | 1 << 17); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1058 | } |
| 1059 | |
| 1060 | write32(&rk3399_pmugrf->os_reg2, sys_reg); |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1061 | DDR_STRIDE(params->stride); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1062 | |
| 1063 | /* reboot hold register set */ |
| 1064 | write32(&pmucru_ptr->pmucru_rstnhold_con[1], |
| 1065 | PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | |
| 1066 | PRESET_GPIO1_HOLD(1)); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 1067 | clrsetbits32(&cru_ptr->glb_rst_con, 0x3, 0x3); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1068 | } |
| 1069 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1070 | static void switch_to_phy_index1(const struct rk3399_sdram_params *params) |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1071 | { |
| 1072 | u32 channel; |
| 1073 | u32 *denali_phy; |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1074 | struct stopwatch sw; |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1075 | u32 ch_count = params->num_channels; |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1076 | |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1077 | stopwatch_init_msecs_expire(&sw, 100); |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1078 | write32(&rk3399_ddr_cic->cic_ctrl0, |
| 1079 | RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, |
| 1080 | 1 << 4 | 1 << 2 | 1)); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1081 | while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) { |
| 1082 | if (stopwatch_expired(&sw)) { |
| 1083 | printk(BIOS_ERR, |
| 1084 | "index1 frequency change overtime, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 1085 | board_reset(); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1086 | } |
| 1087 | } |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1088 | |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1089 | stopwatch_init_msecs_expire(&sw, 100); |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1090 | write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1)); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1091 | while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) { |
| 1092 | if (stopwatch_expired(&sw)) { |
| 1093 | printk(BIOS_ERR, |
| 1094 | "index1 frequency done overtime, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 1095 | board_reset(); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1096 | } |
| 1097 | } |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1098 | |
| 1099 | for (channel = 0; channel < ch_count; channel++) { |
| 1100 | denali_phy = rk3399_ddr_publ[channel]->denali_phy; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 1101 | clrsetbits32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1102 | if (data_training(channel, params, PI_FULL_TRAINING)) { |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1103 | printk(BIOS_ERR, "index1 training failed, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 1104 | board_reset(); |
Lin Huang | 13acd35 | 2016-10-16 13:24:08 -0700 | [diff] [blame] | 1105 | } |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1106 | } |
| 1107 | } |
| 1108 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1109 | void sdram_init(const struct rk3399_sdram_params *params) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1110 | { |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1111 | unsigned char dramtype = params->dramtype; |
| 1112 | unsigned int ddr_freq = params->ddr_freq; |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1113 | int channel; |
| 1114 | |
| 1115 | printk(BIOS_INFO, "Starting SDRAM initialization...\n"); |
| 1116 | |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1117 | if ((dramtype == DDR3 && ddr_freq > 800*MHz) || |
Lin Huang | ba2b63a | 2016-07-25 10:06:09 +0800 | [diff] [blame] | 1118 | (dramtype == LPDDR3 && ddr_freq > 933*MHz) || |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1119 | (dramtype == LPDDR4 && ddr_freq > 800*MHz)) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1120 | die("SDRAM frequency is to high!"); |
| 1121 | |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1122 | rkclk_configure_ddr(ddr_freq); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1123 | |
| 1124 | for (channel = 0; channel < 2; channel++) { |
Moritz Fischer | c73102d | 2021-02-18 14:43:20 -0800 | [diff] [blame] | 1125 | phy_pctrl_reset(channel); |
Moritz Fischer | 619c60f | 2021-02-19 17:56:10 -0800 | [diff] [blame] | 1126 | phy_dll_bypass_set(rk3399_ddr_publ[channel], ddr_freq); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1127 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1128 | if (channel >= params->num_channels) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1129 | continue; |
| 1130 | |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1131 | /* |
| 1132 | * TODO: we need to find the root cause why this |
| 1133 | * step may fail, before that, we just reset the |
| 1134 | * system, and start again. |
| 1135 | */ |
Moritz Fischer | 1e19213 | 2021-02-28 19:26:37 -0800 | [diff] [blame] | 1136 | if (pctl_cfg(channel, params)) { |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1137 | printk(BIOS_ERR, "pctl_cfg fail, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 1138 | board_reset(); |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1139 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1140 | |
| 1141 | /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ |
Derek Basehore | d570a5a | 2016-06-23 14:24:36 -0700 | [diff] [blame] | 1142 | if (dramtype == LPDDR3) |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1143 | udelay(10); |
| 1144 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1145 | if (data_training(channel, params, PI_FULL_TRAINING)) { |
| 1146 | printk(BIOS_ERR, "SDRAM initialization failed, reset\n"); |
Nico Huber | 496fb23 | 2018-10-06 17:56:17 +0200 | [diff] [blame] | 1147 | board_reset(); |
Lin Huang | df3321a | 2016-10-10 20:57:09 -0700 | [diff] [blame] | 1148 | } |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1149 | |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1150 | set_ddrconfig(params, channel, params->ch[channel].ddrconfig); |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1151 | } |
Moritz Fischer | 6410a00 | 2021-02-17 13:29:22 -0800 | [diff] [blame] | 1152 | dram_all_config(params); |
| 1153 | switch_to_phy_index1(params); |
Lin Huang | 883f5cb | 2016-09-15 22:59:55 +0800 | [diff] [blame] | 1154 | |
Lin Huang | c4cbf48 | 2016-03-17 15:28:33 +0800 | [diff] [blame] | 1155 | printk(BIOS_INFO, "Finish SDRAM initialization...\n"); |
| 1156 | } |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 1157 | |
| 1158 | size_t sdram_size_mb(void) |
| 1159 | { |
Lin Huang | f00af58 | 2016-11-15 11:40:58 +0800 | [diff] [blame] | 1160 | u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; |
| 1161 | size_t chipsize_mb = 0; |
| 1162 | static size_t size_mb = 0; |
| 1163 | u32 ch; |
| 1164 | |
| 1165 | if (!size_mb) { |
| 1166 | u32 sys_reg = read32(&rk3399_pmugrf->os_reg2); |
| 1167 | u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg); |
| 1168 | |
| 1169 | for (ch = 0; ch < ch_num; ch++) { |
| 1170 | rank = SYS_REG_DEC_RANK(sys_reg, ch); |
| 1171 | col = SYS_REG_DEC_COL(sys_reg, ch); |
| 1172 | bk = SYS_REG_DEC_BK(sys_reg, ch); |
| 1173 | cs0_row = SYS_REG_DEC_CS0_ROW(sys_reg, ch); |
| 1174 | cs1_row = SYS_REG_DEC_CS1_ROW(sys_reg, ch); |
| 1175 | bw = SYS_REG_DEC_BW(sys_reg, ch); |
| 1176 | row_3_4 = SYS_REG_DEC_ROW_3_4(sys_reg, ch); |
| 1177 | |
| 1178 | chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); |
| 1179 | |
| 1180 | if (rank > 1) |
| 1181 | chipsize_mb += chipsize_mb >> |
| 1182 | (cs0_row - cs1_row); |
| 1183 | if (row_3_4) |
| 1184 | chipsize_mb = chipsize_mb * 3 / 4; |
| 1185 | size_mb += chipsize_mb; |
| 1186 | } |
| 1187 | |
| 1188 | /* |
| 1189 | * we use the 0x00000000~0xf7ffffff space |
| 1190 | * since 0xf8000000~0xffffffff is soc register space |
| 1191 | * so we reserve it |
| 1192 | */ |
| 1193 | size_mb = MIN(size_mb, 0xf8000000/MiB); |
| 1194 | } |
| 1195 | |
| 1196 | return size_mb; |
Shunqian Zheng | 2d3570a | 2016-04-13 21:34:12 +0800 | [diff] [blame] | 1197 | } |