Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <cpu/x86/msr.h> |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 6 | #include <cpu/intel/cpu_ids.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <fsp/util.h> |
| 9 | #include <intelblocks/cpulib.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 10 | #include <intelblocks/pcie_rp.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 11 | #include <soc/gpio_soc_defs.h> |
| 12 | #include <soc/iomap.h> |
| 13 | #include <soc/msr.h> |
| 14 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 15 | #include <soc/pcie.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 16 | #include <soc/romstage.h> |
| 17 | #include <soc/soc_chip.h> |
| 18 | #include <string.h> |
| 19 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 20 | #define FSP_CLK_NOTUSED 0xFF |
| 21 | #define FSP_CLK_LAN 0x70 |
| 22 | #define FSP_CLK_FREE_RUNNING 0x80 |
| 23 | |
| 24 | #define CPU_PCIE_BASE 0x40 |
| 25 | |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 26 | enum vtd_base_index_type { |
| 27 | VTD_GFX, |
| 28 | VTD_IPU, |
| 29 | VTD_VTVCO, |
Sridhar Siricilla | d047927 | 2021-05-28 20:00:02 +0530 | [diff] [blame] | 30 | VTD_TBT0, |
| 31 | VTD_TBT1, |
| 32 | VTD_TBT2, |
| 33 | VTD_TBT3, |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 34 | }; |
| 35 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 36 | static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) |
| 37 | { |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 38 | assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU); |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 39 | |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 40 | if (type == PCIE_RP_PCH) |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 41 | return rp_number; |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 42 | else // type == PCIE_RP_CPU |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 43 | return CPU_PCIE_BASE + rp_number; |
| 44 | } |
| 45 | |
| 46 | static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type, |
| 47 | const struct pcie_rp_config *cfg, size_t cfg_count) |
| 48 | { |
| 49 | size_t i; |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 50 | /* bitmask to save the status of clkreq assignment */ |
| 51 | static unsigned int clk_req_mapping = 0; |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 52 | |
| 53 | for (i = 0; i < cfg_count; i++) { |
| 54 | if (!(en_mask & BIT(i))) |
| 55 | continue; |
| 56 | if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |
| 57 | continue; |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 58 | if (clk_req_mapping & (1 << cfg[i].clk_req)) |
| 59 | printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" |
| 60 | , cfg[i].clk_req); |
| 61 | if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 62 | m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 63 | clk_req_mapping |= 1 << cfg[i].clk_req; |
| 64 | } |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 65 | m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); |
| 66 | } |
| 67 | } |
| 68 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 69 | static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, |
| 70 | const struct soc_intel_alderlake_config *config) |
| 71 | { |
| 72 | /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ |
| 73 | unsigned int i; |
| 74 | |
| 75 | for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { |
| 76 | if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) |
| 77 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 78 | else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) |
| 79 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; |
| 80 | else |
| 81 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; |
| 82 | m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; |
| 83 | } |
| 84 | |
| 85 | /* Configure PCH PCIE ports */ |
| 86 | m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 87 | pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 88 | CONFIG_MAX_PCH_ROOT_PORTS); |
| 89 | |
| 90 | /* Configure CPU PCIE ports */ |
| 91 | m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 92 | pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 93 | CONFIG_MAX_CPU_ROOT_PORTS); |
| 94 | } |
| 95 | |
| 96 | static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 97 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 98 | { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 99 | unsigned int i; |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 100 | const struct ddi_port_upds { |
| 101 | uint8_t *ddc; |
| 102 | uint8_t *hpd; |
| 103 | } ddi_port_upds[] = { |
| 104 | [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, |
| 105 | [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, |
| 106 | [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, |
| 107 | [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, |
| 108 | [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, |
| 109 | [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, |
| 110 | [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, |
| 111 | }; |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 112 | m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 113 | if (m_cfg->InternalGfx) { |
| 114 | /* IGD is enabled, set IGD stolen size to 60MB. */ |
| 115 | m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB; |
| 116 | /* DP port config */ |
| 117 | m_cfg->DdiPortAConfig = config->DdiPortAConfig; |
| 118 | m_cfg->DdiPortBConfig = config->DdiPortBConfig; |
| 119 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 120 | *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & |
| 121 | DDI_ENABLE_DDC); |
| 122 | *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & |
| 123 | DDI_ENABLE_HPD); |
| 124 | } |
| 125 | } else { |
| 126 | /* IGD is disabled, skip IGD init in FSP. */ |
| 127 | m_cfg->IgdDvmt50PreAlloc = 0; |
| 128 | /* DP port config */ |
| 129 | m_cfg->DdiPortAConfig = 0; |
| 130 | m_cfg->DdiPortBConfig = 0; |
| 131 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 132 | *ddi_port_upds[i].ddc = 0; |
| 133 | *ddi_port_upds[i].hpd = 0; |
| 134 | } |
| 135 | } |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 136 | } |
| 137 | static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, |
| 138 | const struct soc_intel_alderlake_config *config) |
| 139 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 140 | m_cfg->SaGv = config->SaGv; |
| 141 | m_cfg->RMT = config->RMT; |
Casper Chang | 8fcefd3 | 2021-09-22 22:35:54 -0400 | [diff] [blame] | 142 | if (config->MaxDramSpeed) |
| 143 | m_cfg->DdrFreqLimit = config->MaxDramSpeed; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 144 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 145 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 146 | static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |
| 147 | const struct soc_intel_alderlake_config *config) |
| 148 | { |
| 149 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 150 | /* CpuRatio Settings */ |
| 151 | if (config->cpu_ratio_override) |
| 152 | m_cfg->CpuRatio = config->cpu_ratio_override; |
| 153 | else |
| 154 | /* Set CpuRatio to match existing MSR value */ |
| 155 | m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; |
| 156 | |
Subrata Banik | 80835a1 | 2020-09-23 17:46:11 +0530 | [diff] [blame] | 157 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 158 | m_cfg->EnableC6Dram = config->enable_c6dram; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 159 | /* Enable Hyper Threading */ |
| 160 | m_cfg->HyperThreading = 1; |
| 161 | } |
| 162 | |
| 163 | static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, |
| 164 | const struct soc_intel_alderlake_config *config) |
| 165 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 166 | /* Disable BIOS Guard */ |
| 167 | m_cfg->BiosGuard = 0; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 168 | m_cfg->TmeEnable = CONFIG(INTEL_TME); |
| 169 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 170 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 171 | static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, |
| 172 | const struct soc_intel_alderlake_config *config) |
| 173 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 174 | /* UART Debug Log */ |
| 175 | m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? |
| 176 | DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; |
| 177 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 178 | m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; |
| 179 | m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; |
| 180 | m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 181 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 182 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 183 | static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, |
| 184 | const struct soc_intel_alderlake_config *config) |
| 185 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 186 | /* Image clock: disable all clocks for bypassing FSP pin mux */ |
| 187 | memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 188 | /* IPU */ |
| 189 | m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); |
| 190 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 191 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 192 | static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, |
| 193 | const struct soc_intel_alderlake_config *config) |
| 194 | { |
| 195 | m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); |
| 196 | } |
| 197 | |
| 198 | static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, |
| 199 | const struct soc_intel_alderlake_config *config) |
| 200 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 201 | /* Disable Lock PCU Thermal Management registers */ |
| 202 | m_cfg->LockPTMregs = 0; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 203 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 204 | /* Skip CPU replacement check */ |
| 205 | m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; |
| 206 | |
| 207 | /* Skip GPIO configuration from FSP */ |
| 208 | m_cfg->GpioOverride = 0x1; |
MAULIK V VAGHELA | 9a7fbbc | 2021-10-13 11:52:17 +0530 | [diff] [blame] | 209 | |
| 210 | /* Skip generation of MBP HOB from FSP. coreboot doesn't consume it */ |
| 211 | m_cfg->SkipMbpHob = 1; |
Ronak Kanabar | fc69b9d | 2021-10-06 13:02:34 +0530 | [diff] [blame] | 212 | |
| 213 | /* CNVi DDR RFI Mitigation */ |
| 214 | m_cfg->CnviDdrRfim = config->CnviDdrRfim; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, |
| 218 | const struct soc_intel_alderlake_config *config) |
| 219 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 220 | /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 221 | m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 222 | m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 223 | m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; |
| 224 | m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; |
| 225 | m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable; |
Furquan Shaikh | c1c1ba5 | 2021-04-20 16:57:59 -0700 | [diff] [blame] | 226 | /* |
| 227 | * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to |
| 228 | * configure GPIO pads for audio. Mainboard is expected to perform all GPIO |
| 229 | * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO |
| 230 | * configuration for audio pads. |
| 231 | */ |
| 232 | m_cfg->PchHdaAudioLinkHdaEnable = 0; |
| 233 | memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); |
| 234 | memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); |
| 235 | memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 236 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 237 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 238 | static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, |
| 239 | const struct soc_intel_alderlake_config *config) |
| 240 | { |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 241 | m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 242 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 243 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 244 | static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, |
| 245 | const struct soc_intel_alderlake_config *config) |
| 246 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 247 | /* Tcss USB */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 248 | m_cfg->TcssXhciEn = is_devfn_enabled(SA_DEVFN_TCSS_XHCI); |
| 249 | m_cfg->TcssXdciEn = is_devfn_enabled(SA_DEVFN_TCSS_XDCI); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 250 | |
| 251 | /* TCSS DMA */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 252 | m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); |
| 253 | m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 254 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 255 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 256 | static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, |
| 257 | const struct soc_intel_alderlake_config *config) |
| 258 | { |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 259 | m_cfg->TcssItbtPcie0En = is_devfn_enabled(SA_DEVFN_TBT0); |
| 260 | m_cfg->TcssItbtPcie1En = is_devfn_enabled(SA_DEVFN_TBT1); |
| 261 | m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2); |
| 262 | m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 263 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 264 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 265 | static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, |
| 266 | const struct soc_intel_alderlake_config *config) |
| 267 | { |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 268 | const uint32_t cpuid = cpu_get_cpuid(); |
| 269 | |
| 270 | /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ |
| 271 | if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1) { |
| 272 | m_cfg->VtdDisable = 1; |
| 273 | return; |
| 274 | } |
| 275 | |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 276 | m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; |
| 277 | m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; |
| 278 | m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; |
| 279 | |
| 280 | m_cfg->VtdDisable = 0; |
| 281 | m_cfg->VtdIopEnable = !m_cfg->VtdDisable; |
| 282 | m_cfg->VtdIgdEnable = m_cfg->InternalGfx; |
| 283 | m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable; |
| 284 | |
| 285 | if (m_cfg->VtdIgdEnable && m_cfg->VtdBaseAddress[VTD_GFX] == 0) { |
| 286 | m_cfg->VtdIgdEnable = 0; |
| 287 | printk(BIOS_ERR, "ERROR: Requested IGD VT-d, but GFXVT_BASE_ADDRESS is 0\n"); |
| 288 | } |
| 289 | |
| 290 | if (m_cfg->VtdIpuEnable && m_cfg->VtdBaseAddress[VTD_IPU] == 0) { |
| 291 | m_cfg->VtdIpuEnable = 0; |
| 292 | printk(BIOS_ERR, "ERROR: Requested IPU VT-d, but IPUVT_BASE_ADDRESS is 0\n"); |
| 293 | } |
| 294 | |
| 295 | if (!m_cfg->VtdDisable && m_cfg->VtdBaseAddress[VTD_VTVCO] == 0) { |
| 296 | m_cfg->VtdDisable = 1; |
| 297 | printk(BIOS_ERR, "ERROR: Requested VT-d, but VTVCO_BASE_ADDRESS is 0\n"); |
| 298 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 299 | |
Sridhar Siricilla | d047927 | 2021-05-28 20:00:02 +0530 | [diff] [blame] | 300 | if (m_cfg->TcssDma0En || m_cfg->TcssDma1En) |
| 301 | m_cfg->VtdItbtEnable = 1; |
| 302 | |
| 303 | if (m_cfg->TcssItbtPcie0En) |
| 304 | m_cfg->VtdBaseAddress[VTD_TBT0] = TBT0_BASE_ADDRESS; |
| 305 | |
| 306 | if (m_cfg->TcssItbtPcie1En) |
| 307 | m_cfg->VtdBaseAddress[VTD_TBT1] = TBT1_BASE_ADDRESS; |
| 308 | |
| 309 | if (m_cfg->TcssItbtPcie2En) |
| 310 | m_cfg->VtdBaseAddress[VTD_TBT2] = TBT2_BASE_ADDRESS; |
| 311 | |
| 312 | if (m_cfg->TcssItbtPcie3En) |
| 313 | m_cfg->VtdBaseAddress[VTD_TBT3] = TBT3_BASE_ADDRESS; |
| 314 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 315 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 316 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 317 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 318 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 319 | static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, |
| 320 | const struct soc_intel_alderlake_config *config) |
| 321 | { |
Subrata Banik | b4a169a | 2021-12-29 18:36:23 +0000 | [diff] [blame] | 322 | /* Set MRC debug level */ |
| 323 | m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level(); |
| 324 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 325 | /* Set debug probe type */ |
| 326 | m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; |
Francois Toguo | cea4f92 | 2021-04-16 21:20:39 -0700 | [diff] [blame] | 327 | |
| 328 | /* CrashLog config */ |
Subrata Banik | 7b8d11b | 2021-07-14 13:11:53 +0530 | [diff] [blame] | 329 | m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); |
| 330 | m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 331 | } |
| 332 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 333 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 334 | const struct soc_intel_alderlake_config *config) |
| 335 | { |
| 336 | const void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, |
| 337 | const struct soc_intel_alderlake_config *config) = { |
| 338 | fill_fspm_igd_params, |
| 339 | fill_fspm_mrc_params, |
| 340 | fill_fspm_cpu_params, |
| 341 | fill_fspm_security_params, |
| 342 | fill_fspm_uart_params, |
| 343 | fill_fspm_ipu_params, |
| 344 | fill_fspm_smbus_params, |
| 345 | fill_fspm_misc_params, |
| 346 | fill_fspm_audio_params, |
| 347 | fill_fspm_pcie_rp_params, |
| 348 | fill_fspm_ish_params, |
| 349 | fill_fspm_tcss_params, |
| 350 | fill_fspm_usb4_params, |
| 351 | fill_fspm_vtd_params, |
| 352 | fill_fspm_trace_params, |
| 353 | }; |
| 354 | |
| 355 | for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) |
| 356 | fill_fspm_params[i](m_cfg, config); |
| 357 | } |
| 358 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 359 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 360 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 361 | const struct soc_intel_alderlake_config *config; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 362 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 363 | |
| 364 | config = config_of_soc(); |
| 365 | |
| 366 | soc_memory_init_params(m_cfg, config); |
Subrata Banik | 0007fa9 | 2021-06-23 15:27:43 +0530 | [diff] [blame] | 367 | mainboard_memory_init_params(m_cfg); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 368 | } |
| 369 | |
Subrata Banik | 0007fa9 | 2021-06-23 15:27:43 +0530 | [diff] [blame] | 370 | __weak void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 371 | { |
| 372 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 373 | } |