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Rob Barnesf892b852021-06-07 08:55:14 -06001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <console/console.h>
4#include <cbmem.h>
5#include <device/device.h>
6#include <device/dram/lpddr4.h>
Rob Barnesf892b852021-06-07 08:55:14 -06007#include <memory_info.h>
8#include <smbios.h>
9#include <types.h>
10
11enum lpddr4_speed_grade {
Rob Barnes4c66daa2021-08-31 15:42:20 -060012 LPDDR4_1333,
Rob Barnesf892b852021-06-07 08:55:14 -060013 LPDDR4_1600,
Rob Barnes4c66daa2021-08-31 15:42:20 -060014 LPDDR4_1866,
15 LPDDR4_2133,
Rob Barnesf892b852021-06-07 08:55:14 -060016 LPDDR4_2400,
Rob Barnes4c66daa2021-08-31 15:42:20 -060017 LPDDR4_2666,
Rob Barnesf892b852021-06-07 08:55:14 -060018 LPDDR4_3200,
Rob Barnes4c66daa2021-08-31 15:42:20 -060019 LPDDR4_3733,
20 LPDDR4_4266,
Rob Barnesf892b852021-06-07 08:55:14 -060021};
22
23struct lpddr4_speed_attr {
24 uint32_t min_clock_mhz; // inclusive
25 uint32_t max_clock_mhz; // inclusive
26 uint32_t reported_mts;
27};
28
29/**
Rob Barnes4c66daa2021-08-31 15:42:20 -060030 * LPDDR4 speed attributes derived from JEDEC 209-4C and industry norms
Rob Barnesf892b852021-06-07 08:55:14 -060031 *
32 * min_clock_mhz = Previous max_clock_mhz + 1
33 * max_clock_mhz = 1000/min_tCk_avg(ns)
34 * reported_mts = Standard reported DDR4 speed in MT/s
35 * May be slightly less than the actual max MT/s
36 */
37static const struct lpddr4_speed_attr lpddr4_speeds[] = {
Rob Barnes4c66daa2021-08-31 15:42:20 -060038 [LPDDR4_1333] = {
Rob Barnesf892b852021-06-07 08:55:14 -060039 .min_clock_mhz = 10,
Rob Barnes4c66daa2021-08-31 15:42:20 -060040 .max_clock_mhz = 667,
41 .reported_mts = 1333,
42 },
43 [LPDDR4_1600] = {
44 .min_clock_mhz = 668,
Rob Barnesf892b852021-06-07 08:55:14 -060045 .max_clock_mhz = 800,
46 .reported_mts = 1600
47 },
Rob Barnes4c66daa2021-08-31 15:42:20 -060048 [LPDDR4_1866] = {
Rob Barnesf892b852021-06-07 08:55:14 -060049 .min_clock_mhz = 801,
Rob Barnes4c66daa2021-08-31 15:42:20 -060050 .max_clock_mhz = 934,
51 .reported_mts = 1866,
52 },
53 [LPDDR4_2133] = {
54 .min_clock_mhz = 935,
55 .max_clock_mhz = 1067,
56 .reported_mts = 2133
57 },
58 [LPDDR4_2400] = {
59 .min_clock_mhz = 1068,
Rob Barnesf892b852021-06-07 08:55:14 -060060 .max_clock_mhz = 1200,
61 .reported_mts = 2400
62 },
Rob Barnes4c66daa2021-08-31 15:42:20 -060063 [LPDDR4_2666] = {
Rob Barnesf892b852021-06-07 08:55:14 -060064 .min_clock_mhz = 1201,
Rob Barnes4c66daa2021-08-31 15:42:20 -060065 .max_clock_mhz = 1333,
66 .reported_mts = 2666
67 },
68 [LPDDR4_3200] = {
69 .min_clock_mhz = 1334,
Rob Barnesf892b852021-06-07 08:55:14 -060070 .max_clock_mhz = 1600,
71 .reported_mts = 3200
72 },
Rob Barnes4c66daa2021-08-31 15:42:20 -060073 [LPDDR4_3733] = {
Rob Barnesf892b852021-06-07 08:55:14 -060074 .min_clock_mhz = 1601,
Rob Barnes4c66daa2021-08-31 15:42:20 -060075 .max_clock_mhz = 1867,
76 .reported_mts = 3733
77 },
78 [LPDDR4_4266] = {
79 .min_clock_mhz = 1868,
80 .max_clock_mhz = 2134,
Rob Barnesf892b852021-06-07 08:55:14 -060081 .reported_mts = 4266
82 },
83};
84
85/**
86 * Converts LPDDR4 clock speed in MHz to the standard reported speed in MT/s
87 */
88uint16_t lpddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz)
89{
90 for (enum lpddr4_speed_grade speed = 0; speed < ARRAY_SIZE(lpddr4_speeds); speed++) {
91 const struct lpddr4_speed_attr *speed_attr = &lpddr4_speeds[speed];
92 if (speed_mhz >= speed_attr->min_clock_mhz &&
93 speed_mhz <= speed_attr->max_clock_mhz) {
94 return speed_attr->reported_mts;
95 }
96 }
Nikolai Vyssotski63e98fc2021-06-25 12:00:48 -050097 printk(BIOS_ERR, "ERROR: LPDDR4 speed of %d MHz is out of range\n", speed_mhz);
Rob Barnesf892b852021-06-07 08:55:14 -060098 return 0;
99}