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review.coreboot.org / coreboot / 264ace99e8f6b380664e1f307c36f90979b9d0ac / . / src / mainboard / siemens / mc_ehl / variants / mc_ehl2 / gpio.c
blob: 91c041756fb27d9ed0eda54f776082d6236f1d22 [file] [log] [blame]
Werner Zeh264ace92021-09-30 13:57:48 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <baseboard/variants.h>
4#include <commonlib/helpers.h>
5
6/* Pad configuration in ramstage*/
7static const struct pad_config gpio_table[] = {
8 /* Community 0 - GpioGroup GPP_B */
9 PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
10 PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
11 PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */
12 PAD_NC(GPP_B9, NONE), /* Not connected */
13 PAD_NC(GPP_B10, NONE), /* Not connected */
14 PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */
15 PAD_NC(GPP_B14, NONE), /* Not connected */
16 PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */
17 PAD_NC(GPP_B18, NONE), /* Not connected */
18 PAD_NC(GPP_B19, NONE), /* Not connected */
19 PAD_NC(GPP_B20, NONE), /* Not connected */
20 PAD_NC(GPP_B21, NONE), /* Not connected */
21 PAD_NC(GPP_B22, NONE), /* Not connected */
22 PAD_NC(GPP_B23, NONE), /* Not connected */
23
24 /* Community 0 - GpioGroup GPP_T */
25 PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */
26 PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */
27 PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
28 PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
29 PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */
30 PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */
31
32 /* Community 0 - GpioGroup GPP_G */
33 PAD_NC(GPP_G8, NONE), /* Not connected */
34 PAD_NC(GPP_G9, NONE), /* Not connected */
35 PAD_NC(GPP_G12, NONE), /* Not connected */
36 PAD_CFG_NF(GPP_G15, NONE, DEEP, NF1), /* ESPI_IO_0 */
37 PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */
38 PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */
39 PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */
40 PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */
41 PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */
42 PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */
43 PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */
44
45 /* Community 1 - GpioGroup GPP_V */
46 PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */
47 PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), /* EMMC_DATA0 */
48 PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), /* EMMC_DATA1 */
49 PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), /* EMMC_DATA2 */
50 PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), /* EMMC_DATA3 */
51 PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), /* EMMC_DATA4 */
52 PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), /* EMMC_DATA5 */
53 PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), /* EMMC_DATA6 */
54 PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */
55 PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */
56 PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */
57 PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */
58
59 /* Community 1 - GpioGroup GPP_H */
60 PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */
61 PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */
62 PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */
63 PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */
64 PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */
65 PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */
66
67 /* Community 1 - GpioGroup GPP_D */
68 PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */
69
70 /* Community 1 - GpioGroup GPP_U */
71 PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */
72 PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */
73 PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */
74 PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */
75 PAD_NC(GPP_U12, NONE), /* Not connected */
76 PAD_NC(GPP_U13, NONE), /* Not connected */
77 PAD_NC(GPP_U16, NONE), /* Not connected */
78 PAD_NC(GPP_U17, NONE), /* Not connected */
79 PAD_NC(GPP_U18, NONE), /* Not connected */
80 PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */
81
82 /* Community 2 - GpioGroup DSW */
83 PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */
84 PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */
85 PAD_NC(GPD7, NONE), /* Not connected */
86 PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */
87
88 /* Community 3 - GpioGroup GPP_S */
89 PAD_NC(GPP_S0, NONE), /* Not connected */
90 PAD_NC(GPP_S1, NONE), /* Not connected */
91
92 /* Community 3 - GpioGroup GPP_A */
93 PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */
94 PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */
95 PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */
96 PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */
97 PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */
98 PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */
99 PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */
100 PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */
101 PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */
102 PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */
103 PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */
104 PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */
105
106 /* Community 4 - GpioGroup GPP_C */
107 PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */
108 PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */
109 PAD_NC(GPP_C5, NONE), /* Not connected */
110 PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
111 PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
112 PAD_NC(GPP_C8, NONE), /* Not connected */
113 PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */
114 PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */
115 PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */
116 PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */
117 PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */
118 PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */
119
120 /* Community 4 - GpioGroup GPP_F */
121 PAD_NC(GPP_F0, NONE), /* Not connected */
122 PAD_NC(GPP_F1, NONE), /* Not connected */
123 PAD_NC(GPP_F2, NONE), /* Not connected */
124 PAD_NC(GPP_F3, NONE), /* Not connected */
125 PAD_NC(GPP_F4, NONE), /* Not connected */
126 PAD_NC(GPP_F5, NONE), /* Not connected */
127 PAD_NC(GPP_F7, NONE), /* Not connected */
128 PAD_NC(GPP_F8, NONE), /* Not connected */
129 PAD_NC(GPP_F10, NONE), /* Not connected */
130 PAD_NC(GPP_F11, NONE), /* Not connected */
131 PAD_NC(GPP_F12, NONE), /* Not connected */
132 PAD_NC(GPP_F13, NONE), /* Not connected */
133 PAD_NC(GPP_F14, NONE), /* Not connected */
134 PAD_NC(GPP_F15, NONE), /* Not connected */
135 PAD_NC(GPP_F16, NONE), /* Not connected */
136 PAD_NC(GPP_F17, NONE), /* Not connected */
137 PAD_NC(GPP_F20, NONE), /* Not connected */
138 PAD_NC(GPP_F21, NONE), /* Not connected */
139
140 /* Community 4 - GpioGroup GPP_E */
141 PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */
142 PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */
143 PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */
144 PAD_NC(GPP_E6, NONE), /* Not connected */
145 PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */
146 PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */
147 PAD_NC(GPP_E15, NONE), /* Not connected */
148 PAD_NC(GPP_E16, NONE), /* Not connected */
149 PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */
150 PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */
151 PAD_NC(GPP_E23, NONE), /* Not connected */
152
153 /* Community 5 - GpioGroup GPP_R */
154 PAD_NC(GPP_R1, NONE), /* Not connected */
155 PAD_NC(GPP_R2, NONE), /* Not connected */
156 PAD_NC(GPP_R3, NONE), /* Not connected */
157};
158
159/* Early pad configuration in bootblock */
160static const struct pad_config early_gpio_table[] = {
161 PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
162 PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
163 PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2), /* SMB_ALERT_N */
164 PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), /* SIO_UART2_RXD */
165 PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), /* SIO_UART2_TXD */
166};
167
168const struct pad_config *variant_gpio_table(size_t *num)
169{
170 *num = ARRAY_SIZE(gpio_table);
171 return gpio_table;
172}
173
174const struct pad_config *variant_early_gpio_table(size_t *num)
175{
176 *num = ARRAY_SIZE(early_gpio_table);
177 return early_gpio_table;
178}