Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <types.h> |
| 6 | #include <soc/gpio.h> |
| 7 | #include <vendorcode/google/chromeos/chromeos.h> |
| 8 | |
| 9 | /* Pad configuration in ramstage */ |
| 10 | static const struct pad_config gpio_table[] = { |
| 11 | /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */ |
| 12 | /* GPP_A0 : [] ==> ESPI_PCH_D0_EC */ |
| 13 | /* GPP_A1 : [] ==> ESPI_PCH_D1_EC */ |
| 14 | /* GPP_A2 : [] ==> ESPI_PCH_D2_EC */ |
| 15 | /* GPP_A3 : [] ==> ESPI_PCH_D3_EC */ |
| 16 | /* GPP_A4 : [] ==> ESPI_PCH_CS_EC_L */ |
| 17 | /* GPP_A5 : [] ==> TP101 */ |
| 18 | PAD_NC(GPP_A5, NONE), |
| 19 | /* GPP_A6 : [] ==> TP102 */ |
| 20 | PAD_NC(GPP_A6, NONE), |
| 21 | /* GPP_A7 : [] ==> PCIE_LAN_WAKE_ODL */ |
| 22 | PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE), |
| 23 | /* GPP_A8 : [] ==> USB_A1_RT_RST_ODL */ |
| 24 | PAD_CFG_GPO(GPP_A8, 1, DEEP), |
| 25 | /* GPP_A9 : [] ==> ESPI_PCH_CLK */ |
| 26 | /* GPP_A10 : [] ==> ESPI_PCH_RST_EC_L */ |
| 27 | /* GPP_A11 : [] ==> EN_SPKR_PA */ |
| 28 | PAD_CFG_GPO(GPP_A11, 1, DEEP), |
| 29 | /* GPP_A12 : [] ==> EN_PP3300_LAN_X */ |
| 30 | PAD_CFG_GPO(GPP_A12, 1, DEEP), |
Tarun Tuli | 15dd44e | 2023-04-14 19:32:24 +0000 | [diff] [blame] | 31 | /* GPP_A13 : [] ==> BT_DISABLE_L */ |
| 32 | PAD_CFG_GPO(GPP_A13, 1, DEEP), |
Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 33 | /* GPP_A14 : [] ==> EC_USB_PCH_C0_OC_ODL */ |
| 34 | PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), |
| 35 | /* GPP_A15 : [] ==> EC_USB_PCH_C1_OC_ODL */ |
| 36 | PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), |
| 37 | /* GPP_A16 : [] ==> USB_A0_OC_ODL */ |
| 38 | PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG), |
| 39 | /* GPP_A17 : [] ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */ |
| 40 | PAD_CFG_GPI(GPP_A17, NONE, PLTRST), |
| 41 | /* GPP_A18 : [] ==> HDMI_HPD */ |
| 42 | PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), |
| 43 | /* GPP_A19 : [] ==> EN_PCH_PPVAR_GPU_FBVDDQ_X */ |
| 44 | PAD_CFG_GPO(GPP_A19, 0, PLTRST), |
Tarun Tuli | 15dd44e | 2023-04-14 19:32:24 +0000 | [diff] [blame] | 45 | /* GPP_A20 : [] ==> GSC_PCH_INT_ODL */ |
| 46 | PAD_CFG_GPI_APIC_LOCK(GPP_A20, NONE, LEVEL, INVERT, LOCK_CONFIG), |
Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 47 | /* GPP_A21 : [] ==> NC */ |
| 48 | PAD_NC(GPP_A21, NONE), |
| 49 | /* GPP_A22 : [] ==> NC */ |
| 50 | PAD_NC(GPP_A22, NONE), |
| 51 | /* GPP_A23 : [] ==> HP_INT_L */ |
Eran Mitrani | 24ca5ef | 2023-05-08 11:56:13 -0700 | [diff] [blame^] | 52 | PAD_CFG_GPI_INT(GPP_A23, UP_20K, PLTRST, EDGE_BOTH), |
Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 53 | |
| 54 | /* GPP_B0 : [] ==> SOC_VID0 */ |
| 55 | PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), |
| 56 | /* GPP_B1 : [] ==> SOC_VID1 */ |
| 57 | PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), |
| 58 | /* GPP_B2 : [] ==> NC */ |
| 59 | PAD_NC(GPP_B2, NONE), |
| 60 | /* GPP_B3 : [] ==> GPU_PERST_L */ |
| 61 | PAD_CFG_GPO(GPP_B3, 0, PLTRST), |
| 62 | /* GPP_B4 : [] ==> SSD_PERST_L */ |
| 63 | PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), |
| 64 | /* GPP_B5 : [] ==> PCH_I2C_NVVDD_GPU_R_SDA */ |
| 65 | PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), |
| 66 | /* GPP_B6 : [] ==> PCH_I2C_NVVDD_GPU_R_SCL */ |
| 67 | PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), |
| 68 | /* GPP_B7 : [] ==> PCH_I2C_TPM_R_SDA */ |
| 69 | PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), |
| 70 | /* GPP_B8 : [] ==> PCH_I2C_TPM_R_SCL */ |
| 71 | PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), |
| 72 | /* GPP_B9 : [] ==> NC */ |
| 73 | PAD_NC(GPP_B9, NONE), |
| 74 | /* GPP_B10 : [] ==> NC */ |
| 75 | PAD_NC(GPP_B10, NONE), |
| 76 | /* GPP_B11 : [] ==> EN_PP3300_WLAN */ |
| 77 | PAD_CFG_GPO(GPP_B11, 1, DEEP), |
| 78 | /* GPP_B12 : [] ==> SLP_S0_L */ |
| 79 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 80 | /* GPP_B13 : [] ==> PLT_RST_L */ |
| 81 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 82 | /* GPP_B14 : [] ==> GPP_B14_STRAP */ |
| 83 | PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG), |
| 84 | /* GPP_B15 : [] ==> NC */ |
| 85 | PAD_NC(GPP_B15, NONE), |
| 86 | /* GPP_B16 : [] ==> PCH_I2C_TCHPAD_SDA */ |
| 87 | PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), |
| 88 | /* GPP_B17 : [] ==> PCH_I2C_TCHPAD_SCL */ |
| 89 | PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), |
| 90 | /* GPP_B18 : [] ==> GPP_B18_STRAP */ |
| 91 | PAD_NC(GPP_B18, NONE), |
| 92 | /* GPP_B19 : [] ==> NC */ |
| 93 | PAD_NC(GPP_B19, NONE), |
| 94 | /* GPP_B20 : [] ==> NC */ |
| 95 | PAD_NC(GPP_B20, NONE), |
| 96 | /* GPP_B21 : [] ==> NC */ |
| 97 | PAD_NC(GPP_B21, NONE), |
| 98 | /* GPP_B22 : [] ==> NC */ |
| 99 | PAD_NC(GPP_B22, NONE), |
| 100 | /* GPP_B23 : [] ==> PCHHOT_ODL_STRAP */ |
| 101 | PAD_NC(GPP_B23, NONE), |
| 102 | |
| 103 | /* GPP_C0 : [] ==> PCH_SMB_CLK */ |
| 104 | PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), |
| 105 | /* GPP_C1 : [] ==> PCH_SMB_DATA */ |
| 106 | PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), |
| 107 | /* GPP_C2 : [] ==> GPP_C2_STRAP */ |
| 108 | PAD_NC(GPP_C2, NONE), |
| 109 | /* GPP_C3 : [] ==> NC */ |
| 110 | PAD_NC(GPP_C3, NONE), |
| 111 | /* GPP_C4 : [] ==> NC */ |
| 112 | PAD_NC(GPP_C4, NONE), |
| 113 | /* GPP_C5 : [] ==> GPP_C5_BOOT_STRAP0 */ |
| 114 | PAD_NC(GPP_C5, NONE), |
| 115 | /* GPP_C6 : [] ==> NC */ |
| 116 | PAD_NC(GPP_C6, NONE), |
| 117 | /* GPP_C7 : [] ==> NC */ |
| 118 | PAD_NC(GPP_C7, NONE), |
| 119 | |
| 120 | /* GPP_D0 : [] ==> EN_PP1200_GPU_X */ |
| 121 | PAD_CFG_GPO(GPP_D0, 0, PLTRST), |
| 122 | /* GPP_D1 : [] ==> PG_PP1200_GPU_X_OD */ |
| 123 | PAD_CFG_GPI(GPP_D1, NONE, DEEP), |
| 124 | /* GPP_D2 : [] ==> LAN_PE_ISOLATE_ODL */ |
| 125 | PAD_CFG_GPO(GPP_D2, 1, DEEP), |
| 126 | /* GPP_D3 : [] ==> PS_NVVDD_TALERT_ODL */ |
| 127 | PAD_CFG_GPI(GPP_D3, NONE, PLTRST), |
Tarun Tuli | 15dd44e | 2023-04-14 19:32:24 +0000 | [diff] [blame] | 128 | /* GPP_D4 : [] ==> NC */ |
| 129 | PAD_NC(GPP_D4, NONE), |
Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 130 | /* GPP_D5 : [] ==> GPU_CLKREQ_ODL */ |
| 131 | PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), |
| 132 | /* GPP_D6 : [] ==> PCIE_SSD_CLKREQ_ODL */ |
| 133 | PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), |
| 134 | /* GPP_D7 : [] ==> PCIE_WLAN_CLKREQ_ODL */ |
| 135 | PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), |
| 136 | /* GPP_D8 : [] ==> PCIE_SD_CLKREQ_ODL */ |
| 137 | PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), |
| 138 | /* GPP_D9 : [] ==> GPU_THERM_INT_ODL */ |
| 139 | PAD_CFG_GPI(GPP_D9, NONE, PLTRST), |
| 140 | /* GPP_D10 : [] ==> GPP_D10_STRAP */ |
| 141 | PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), |
| 142 | /* GPP_D11 : [] ==> EN_PP3300_SSD */ |
| 143 | PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), |
| 144 | /* GPP_D12 : [] ==> GPP_D12_STRAP */ |
| 145 | PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), |
| 146 | /* GPP_D13 : [] ==> NC */ |
| 147 | PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), |
| 148 | /* GPP_D14 : [] ==> NC */ |
| 149 | PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG), |
| 150 | /* GPP_D15 : [] ==> NC */ |
| 151 | PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), |
| 152 | /* GPP_D16 : [] ==> NC */ |
| 153 | PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), |
| 154 | /* GPP_D17 : [] ==> SD_PE_PRSNT_L */ |
| 155 | PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), |
| 156 | /* GPP_D18 : [] ==> SD_PE_RST_L */ |
| 157 | PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), |
| 158 | /* GPP_D19 : [] ==> I2S_MCLK_R */ |
| 159 | PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), |
| 160 | |
| 161 | /* GPP_E0 : [] ==> EN_PPVAR_GPU_NVVDD_X */ |
| 162 | PAD_CFG_GPO(GPP_E0, 0, DEEP), |
| 163 | /* GPP_E1 : [] ==> EN_PP3300_GPU_X */ |
| 164 | PAD_CFG_GPO(GPP_E1, 0, PLTRST), |
| 165 | /* GPP_E2 : [] ==> PG_PP3300_GPU_X_OD */ |
| 166 | PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), |
Tarun Tuli | 15dd44e | 2023-04-14 19:32:24 +0000 | [diff] [blame] | 167 | /* GPP_E3 : [] ==> WIFI_DISABLE_L */ |
| 168 | PAD_CFG_GPO(GPP_E3, 1, DEEP), |
Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 169 | /* GPP_E4 : [] ==> PG_PPVAR_GPU_FBVDDQ_X_OD */ |
| 170 | PAD_CFG_GPI(GPP_E4, NONE, DEEP), |
| 171 | /* GPP_E5 : [] ==> PG_GPU_ALLRAILS */ |
| 172 | PAD_CFG_GPO(GPP_E5, 0, PLTRST), |
| 173 | /* GPP_E6 : [] ==> GPPE6_STRAP */ |
| 174 | PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), |
| 175 | /* GPP_E7 : [] ==> NC */ |
| 176 | PAD_NC(GPP_E7, NONE), |
Tarun Tuli | 15dd44e | 2023-04-14 19:32:24 +0000 | [diff] [blame] | 177 | /* GPP_E8 : [] ==> PG_PPVAR_GPU_NVVDD_X_OD */ |
| 178 | PAD_CFG_GPI(GPP_E8, NONE, DEEP), |
Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 179 | /* GPP_E9 : [] ==> USB_A1_OC_ODL */ |
| 180 | PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), |
| 181 | /* GPP_E10 : [] ==> EN_PPVAR_PEXVDD_GPU_X */ |
| 182 | PAD_CFG_GPO(GPP_E10, 0, PLTRST), |
| 183 | /* GPP_E11 : [] ==> EN_PP1800_GPU_X */ |
| 184 | PAD_CFG_GPO(GPP_E11, 0, PLTRST), |
| 185 | /* GPP_E12 : [] ==> PCH_WP_OD */ |
| 186 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), |
| 187 | /* GPP_E13 : [] ==> NC */ |
| 188 | PAD_NC(GPP_E13, NONE), |
| 189 | /* GPP_E14 : [] ==> SOC_EDP_HPD */ |
| 190 | PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), |
| 191 | /* GPP_E15 : [] ==> NC */ |
| 192 | PAD_NC(GPP_E15, NONE), |
| 193 | /* GPP_E16 : [] ==> NC */ |
| 194 | PAD_CFG_GPI(GPP_E16, NONE, DEEP), |
| 195 | /* GPP_E17 : [] ==> PG_PP0950_GPU_X_OD */ |
| 196 | PAD_CFG_GPI(GPP_E17, NONE, DEEP), |
| 197 | /* GPP_E18 : [] ==> EN_PP1800_GPU_X */ |
| 198 | PAD_CFG_GPO_LOCK(GPP_E18, 0, LOCK_CONFIG), |
| 199 | /* GPP_E19 : [] ==> GPP_E19_STRAP */ |
| 200 | PAD_NC(GPP_E19, NONE), |
| 201 | /* GPP_E20 : [] ==> PG_PP1800_GPU_X_OD */ |
| 202 | PAD_CFG_GPI(GPP_E20, NONE, DEEP), |
| 203 | /* GPP_E21 : [] ==> GPP_E21_STRAP */ |
| 204 | PAD_NC(GPP_E21, NONE), |
| 205 | /* GPP_E22 : [] ==> GPP_E22_DNX_FRCE_RLD_STRAP */ |
| 206 | PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), |
| 207 | /* GPP_E23 : [] ==> GPP_E23_TP */ |
| 208 | PAD_NC(GPP_E23, NONE), |
| 209 | |
| 210 | /* GPP_F0 : [] ==> CNV_BRI_DT_STRAP */ |
| 211 | PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), |
| 212 | /* GPP_F1 : [] ==> CNV_BRI_RSP */ |
| 213 | PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), |
| 214 | /* GPP_F2 : [] ==> CNV_RGI_DT_STRAP */ |
| 215 | PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), |
| 216 | /* GPP_F3 : [] ==> CNV_RGI_RSP */ |
| 217 | PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), |
| 218 | /* GPP_F4 : [] ==> CNV_RF_RST_L */ |
| 219 | PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), |
| 220 | /* GPP_F5 : [] ==> CNV_CLKREQ0 */ |
| 221 | PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), |
| 222 | /* GPP_F6 : [] ==> NC */ |
| 223 | PAD_NC(GPP_F6, NONE), |
| 224 | /* GPP_F7 : [] ==> GPPF7_STRAP */ |
| 225 | PAD_NC(GPP_F7, NONE), |
| 226 | /* GPP_F8 : [] ==> NC */ |
| 227 | PAD_NC(GPP_F8, NONE), |
| 228 | /* GPP_F9 : [] ==> SLP_S0_GATE_R */ |
| 229 | PAD_CFG_GPO(GPP_F9, 1, PLTRST), |
| 230 | /* GPP_F10 : [] ==> GPPF10_STRAP */ |
| 231 | PAD_NC(GPP_F10, DN_20K), |
| 232 | /* GPP_F11 : [] ==> NC */ |
| 233 | PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), |
| 234 | /* GPP_F12 : [] ==> NC */ |
| 235 | PAD_NC(GPP_F12, NONE), |
| 236 | /* GPP_F13 : [] ==> NC */ |
| 237 | PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), |
| 238 | /* GPP_F14 : [] ==> TCHPAD_INT_ODL */ |
| 239 | PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT), |
| 240 | /* GPP_F15 : [] ==> NC */ |
| 241 | PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), |
| 242 | /* GPP_F16 : [] ==> NC */ |
| 243 | PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), |
| 244 | /* GPP_F17 : [] ==> EC_PCH_INT_ODL */ |
| 245 | PAD_CFG_GPI_APIC_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 246 | /* GPP_F18 : [] ==> EC_IN_RW_OD */ |
| 247 | PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), |
| 248 | /* GPP_F19 : [] ==> NC */ |
| 249 | PAD_NC(GPP_F19, NONE), |
| 250 | /* GPP_F20 : [] ==> NC */ |
| 251 | PAD_NC(GPP_F20, NONE), |
| 252 | /* GPP_F21 : [] ==> NC */ |
| 253 | PAD_NC(GPP_F21, NONE), |
| 254 | /* GPP_F22 : [] ==> NC */ |
| 255 | PAD_NC(GPP_F22, NONE), |
| 256 | /* GPP_F23 : [] ==> NC */ |
| 257 | PAD_NC(GPP_F23, NONE), |
| 258 | |
| 259 | /* GPP_H0 : [] ==> GPPH0_BOOT_STRAP1 */ |
| 260 | PAD_NC(GPP_H0, NONE), |
| 261 | /* GPP_H1 : [] ==> GPPH1_BOOT_STRAP2 */ |
| 262 | PAD_NC(GPP_H1, NONE), |
| 263 | /* GPP_H2 : [] ==> GPPH2_BOOT_STRAP3 */ |
| 264 | PAD_NC(GPP_H2, NONE), |
| 265 | /* GPP_H3 : [] ==> WLAN_PCIE_WAKE_ODL */ |
| 266 | PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG), |
| 267 | /* GPP_H4 : [] ==> PCH_I2C_AUD_SDA */ |
| 268 | PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), |
| 269 | /* GPP_H5 : [] ==> PCH_I2C_AUD_SCL */ |
| 270 | PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), |
| 271 | /* GPP_H6 : [] ==> PCH_I2C_GPU_SDA */ |
| 272 | PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), |
| 273 | /* GPP_H7 : [] ==> PCH_I2C_GPU_SCL */ |
| 274 | PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), |
| 275 | /* GPP_H8 : [] ==> NC */ |
| 276 | PAD_NC(GPP_H8, NONE), |
| 277 | /* GPP_H9 : [] ==> NC */ |
| 278 | PAD_NC(GPP_H9, NONE), |
| 279 | /* GPP_H10 : [] ==> UART_PCH_RX_DBG_TX */ |
| 280 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 281 | /* GPP_H11 : [] ==> UART_PCH_TX_DBG_RX */ |
| 282 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
| 283 | /* GPP_H12 : [] ==> SD_PE_WAKE_ODL */ |
| 284 | PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG), |
| 285 | /* GPP_H13 : [] ==> EN_PP3300_SD */ |
| 286 | PAD_CFG_GPO(GPP_H13, 1, PLTRST), |
| 287 | /* GPP_H14 : [] ==> NC */ |
| 288 | PAD_NC(GPP_H14, NONE), |
| 289 | /* GPP_H15 : [] ==> DDIB_HDMI_CTRLCLK */ |
| 290 | PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), |
| 291 | /* GPP_H16 : [] ==> NC */ |
| 292 | PAD_NC(GPP_H16, NONE), |
| 293 | /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ |
| 294 | PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), |
| 295 | /* GPP_H18 : [] ==> CPU_C10_GATE_L */ |
| 296 | PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), |
| 297 | /* GPP_H19 : [] ==> LAN_CLKREQ_ODL */ |
| 298 | PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), |
| 299 | /* GPP_H20 : [] ==> WLAN_PERST_L */ |
| 300 | PAD_CFG_GPO(GPP_H20, 1, DEEP), |
| 301 | /* GPP_H21 : [] ==> NC */ |
| 302 | PAD_NC(GPP_H21, NONE), |
| 303 | /* GPP_H22 : [] ==> NC */ |
| 304 | PAD_NC(GPP_H22, NONE), |
| 305 | /* GPP_H23 : [] ==> WWAN_CLKREQ_ODL */ |
| 306 | PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), |
| 307 | |
| 308 | /* GPP_R0 : [] ==> I2S_HP_SCLK_R */ |
| 309 | PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), |
| 310 | /* GPP_R1 : [] ==> I2S_HP_SFRM_R */ |
| 311 | PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), |
| 312 | /* GPP_R2 : [] ==> I2S_PCH_TX_HP_RX_STRAP */ |
| 313 | PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), |
| 314 | /* GPP_R3 : [] ==> I2S_PCH_RX_HP_TX */ |
| 315 | PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), |
| 316 | /* GPP_R4 : [] ==> DMIC_CLK0 */ |
| 317 | PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), |
| 318 | /* GPP_R5 : [] ==> DMIC_DATA0 */ |
| 319 | PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), |
| 320 | /* GPP_R6 : [] ==> NC */ |
| 321 | PAD_NC(GPP_R6, NONE), |
| 322 | /* GPP_R7 : [] ==> NC */ |
| 323 | PAD_NC(GPP_R7, NONE), |
| 324 | |
| 325 | /* GPP_S0 : [] ==> I2S_SPKR_SCLK */ |
| 326 | PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), |
| 327 | /* GPP_S1 : [] ==> I2S_SPKR_SFRM */ |
| 328 | PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), |
| 329 | /* GPP_S2 : [] ==> I2S_PCH_SPKR_RX */ |
| 330 | PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), |
| 331 | /* GPP_S3 : [] ==> NC */ |
| 332 | PAD_NC(GPP_S3, NONE), |
| 333 | /* GPP_S4 : [] ==> NC */ |
| 334 | PAD_NC(GPP_S4, NONE), |
| 335 | /* GPP_S5 : [] ==> NC */ |
| 336 | PAD_NC(GPP_S5, NONE), |
| 337 | /* GPP_S6 : [] ==> NC */ |
| 338 | PAD_NC(GPP_S6, NONE), |
| 339 | /* GPP_S7 : [] ==> NC */ |
| 340 | PAD_NC(GPP_S7, NONE), |
| 341 | |
| 342 | /* GPD0: [] ==> BATLOW_L */ |
| 343 | PAD_CFG_NF(GPD0, NONE, DEEP, NF1), |
| 344 | /* GPD1: [] ==> PCH_ACPRESENT */ |
| 345 | PAD_CFG_NF(GPD1, NONE, DEEP, NF1), |
| 346 | /* GPD2 : [] ==> EC_PCH_WAKE_ODL */ |
| 347 | PAD_CFG_NF(GPD2, NONE, DEEP, NF1), |
| 348 | /* GPD3: [] ==> EC_PCH_PWR_BTN_ODL */ |
| 349 | PAD_CFG_NF(GPD3, NONE, DEEP, NF1), |
| 350 | /* GPD4: [] ==> SLP_S3_L */ |
| 351 | PAD_CFG_NF(GPD4, NONE, DEEP, NF1), |
| 352 | /* GPD5: [] ==> SLP_S4_L */ |
| 353 | PAD_CFG_NF(GPD5, NONE, DEEP, NF1), |
| 354 | /* GPD6: [] ==> SLP_A_L */ |
| 355 | PAD_CFG_NF(GPD6, NONE, DEEP, NF1), |
| 356 | /* GPD7: [] ==> GPD7_STRAP */ |
| 357 | PAD_NC(GPD7, NONE), |
| 358 | /* GPD8: [] ==> PCH_SUSCLK */ |
| 359 | PAD_CFG_NF(GPD8, NONE, DEEP, NF1), |
| 360 | /* GPD9: [] ==> SLP_WLAN_L */ |
| 361 | PAD_CFG_NF(GPD9, NONE, DEEP, NF1), |
| 362 | /* GPD10: [] ==> SLP_S5_L */ |
| 363 | PAD_CFG_NF(GPD10, NONE, DEEP, NF1), |
| 364 | /* GPD11: [] ==> WWAN_CONFIG1 */ |
| 365 | PAD_NC(GPD11, NONE), |
| 366 | |
| 367 | /* Virtual GPIO */ |
| 368 | /* Put unused Cnvi BT UART lines in NC mode since we use USB mode. */ |
| 369 | PAD_NC(GPP_VGPIO_6, NONE), |
| 370 | PAD_NC(GPP_VGPIO_7, NONE), |
| 371 | PAD_NC(GPP_VGPIO_8, NONE), |
| 372 | PAD_NC(GPP_VGPIO_9, NONE), |
| 373 | |
| 374 | /* Put unused Cnvi UART0 lines in NC mode since we use USB mode. */ |
| 375 | PAD_NC(GPP_VGPIO_18, NONE), |
| 376 | PAD_NC(GPP_VGPIO_19, NONE), |
| 377 | PAD_NC(GPP_VGPIO_20, NONE), |
| 378 | PAD_NC(GPP_VGPIO_21, NONE), |
| 379 | }; |
| 380 | |
| 381 | /* Early pad configuration in bootblock */ |
| 382 | static const struct pad_config early_gpio_table[] = { |
| 383 | /* GPP_A12 : [] ==> EN_PPVAR_WWAN */ |
| 384 | PAD_CFG_GPO(GPP_A12, 1, DEEP), |
| 385 | /* GPP_A13 : [] ==> GSC_PCH_INT_ODL */ |
Eric Lai | 909829e | 2023-05-13 15:43:07 +0800 | [diff] [blame] | 386 | PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), |
Tarun Tuli | 8f5295c | 2023-02-17 14:07:11 +0000 | [diff] [blame] | 387 | /* GPP_B4 : [] ==> SSD_PERST_L */ |
| 388 | PAD_CFG_GPO(GPP_B4, 0, DEEP), |
| 389 | /* GPP_B7 : [] ==> PCH_I2C_TPM_SDA */ |
| 390 | PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), |
| 391 | /* GPP_B8 : [] ==> PCH_I2C_TPM_SCL */ |
| 392 | PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), |
| 393 | /* |
| 394 | * GPP_D1 : [] ==> FP_RST_ODL |
| 395 | * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. |
| 396 | * To ensure proper power sequencing for the FPMCU device, reset signal is driven low |
| 397 | * early on in bootblock, followed by enabling of power. Reset signal is deasserted |
| 398 | * later on in ramstage. Since reset signal is asserted in bootblock, it results in |
| 399 | * FPMCU not working after a S3 resume. This is a known issue. |
| 400 | */ |
| 401 | PAD_CFG_GPO(GPP_D1, 0, DEEP), |
| 402 | /* GPP_D2 : [] ==> EN_FP_PWR */ |
| 403 | PAD_CFG_GPO(GPP_D2, 1, DEEP), |
| 404 | /* GPP_D11 : [] ==> EN_PP3300_SSD */ |
| 405 | PAD_CFG_GPO(GPP_D11, 1, PLTRST), |
| 406 | /* GPP_E13 : [] ==> MEM_CH_SEL */ |
| 407 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 408 | /* GPP_E15 : [] ==> PCH_WP_OD */ |
| 409 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), |
| 410 | /* GPP_E16 : [] ==> WWAN_RST_L |
| 411 | * To meet timing constrains - drive reset low. |
| 412 | * Deasserted in ramstage. |
| 413 | */ |
| 414 | PAD_CFG_GPO(GPP_E16, 0, DEEP), |
| 415 | /* GPP_E15 : [] ==> PCH_WP_OD */ |
| 416 | PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), |
| 417 | /* GPP_E18 : [] ==> EN_PP1800_GPU_X */ |
| 418 | PAD_CFG_GPO(GPP_E18, 0, PLTRST), |
| 419 | /* GPP_F18 : [] ==> EC_IN_RW_OD */ |
| 420 | PAD_CFG_GPI(GPP_F18, NONE, DEEP), |
| 421 | /* GPP_H10 : [] ==> UART_PCH_RX_DBG_TX */ |
| 422 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 423 | /* GPP_H11 : [] ==> UART_PCH_TX_DBG_RX */ |
| 424 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
| 425 | /* |
| 426 | * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and |
| 427 | * then deassert PERST# in romstage |
| 428 | */ |
| 429 | /* GPP_H13 : [] ==> EN_PP3300_SD */ |
| 430 | PAD_CFG_GPO(GPP_H13, 1, PLTRST), |
| 431 | /* GPP_B4 : [] ==> SSD_PERST_L */ |
| 432 | PAD_CFG_GPO(GPP_B4, 0, DEEP), |
| 433 | |
| 434 | /* CPU PCIe VGPIO for PEG60 */ |
| 435 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), |
| 436 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), |
| 437 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), |
| 438 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), |
| 439 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), |
| 440 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), |
| 441 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), |
| 442 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), |
| 443 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), |
| 444 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), |
| 445 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), |
| 446 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), |
| 447 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), |
| 448 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), |
| 449 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), |
| 450 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), |
| 451 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), |
| 452 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), |
| 453 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), |
| 454 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), |
| 455 | }; |
| 456 | |
| 457 | const struct pad_config *variant_gpio_table(size_t *num) |
| 458 | { |
| 459 | *num = ARRAY_SIZE(gpio_table); |
| 460 | return gpio_table; |
| 461 | } |
| 462 | |
| 463 | const struct pad_config *variant_gpio_override_table(size_t *num) |
| 464 | { |
| 465 | *num = 0; |
| 466 | return NULL; |
| 467 | } |
| 468 | |
| 469 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 470 | { |
| 471 | *num = ARRAY_SIZE(early_gpio_table); |
| 472 | return early_gpio_table; |
| 473 | } |
| 474 | |
| 475 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 476 | { |
| 477 | *num = 0; |
| 478 | return NULL; |
| 479 | } |
| 480 | |
| 481 | static const struct cros_gpio cros_gpios[] = { |
| 482 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 483 | CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), |
| 484 | }; |
| 485 | |
| 486 | DECLARE_WEAK_CROS_GPIOS(cros_gpios); |