| zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | |
| 22 | #include <arch/io.h> |
| 23 | #include <arch/acpi.h> |
| 24 | |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <device/pci_ops.h> |
| 29 | #include <cbmem.h> |
| 30 | #include "hudson.h" |
| 31 | #include "smbus.h" |
| 32 | |
| 33 | #if CONFIG_HAVE_ACPI_RESUME == 1 |
| 34 | int acpi_get_sleep_type(void) |
| 35 | { |
| 36 | u16 tmp = inw(PM1_CNT_BLK_ADDRESS); |
| 37 | tmp = ((tmp & (7 << 10)) >> 10); |
| 38 | /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ |
| 39 | return (int)tmp; |
| 40 | } |
| 41 | #endif |
| 42 | |
| 43 | void set_cbmem_toc(struct cbmem_entry *toc) |
| 44 | { |
| 45 | u32 dword = (u32) toc; |
| 46 | int nvram_pos = 0xf8, i; /* temp */ |
| 47 | /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ |
| 48 | for (i = 0; i<4; i++) { |
| 49 | /* printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); */ |
| 50 | outb(nvram_pos, BIOSRAM_INDEX); |
| 51 | outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); |
| 52 | nvram_pos++; |
| 53 | } |
| 54 | } |
| 55 | |
| 56 | void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) |
| 57 | { |
| 58 | u32 reg_old, reg; |
| 59 | reg = reg_old = pci_read_config32(sm_dev, reg_pos); |
| 60 | reg &= ~mask; |
| 61 | reg |= val; |
| 62 | if (reg != reg_old) { |
| 63 | pci_write_config32(sm_dev, reg_pos, reg); |
| 64 | } |
| 65 | } |
| 66 | |
| 67 | static void pmio_write_index(u16 port_base, u8 reg, u8 value) |
| 68 | { |
| 69 | outb(reg, port_base); |
| 70 | outb(value, port_base + 1); |
| 71 | } |
| 72 | |
| 73 | static u8 pmio_read_index(u16 port_base, u8 reg) |
| 74 | { |
| 75 | outb(reg, port_base); |
| 76 | return inb(port_base + 1); |
| 77 | } |
| 78 | |
| 79 | void pm_iowrite(u8 reg, u8 value) |
| 80 | { |
| 81 | pmio_write_index(PM_INDEX, reg, value); |
| 82 | } |
| 83 | |
| 84 | u8 pm_ioread(u8 reg) |
| 85 | { |
| 86 | return pmio_read_index(PM_INDEX, reg); |
| 87 | } |
| 88 | |
| 89 | void pm2_iowrite(u8 reg, u8 value) |
| 90 | { |
| 91 | pmio_write_index(PM2_INDEX, reg, value); |
| 92 | } |
| 93 | |
| 94 | u8 pm2_ioread(u8 reg) |
| 95 | { |
| 96 | return pmio_read_index(PM2_INDEX, reg); |
| 97 | } |
| 98 | |
| 99 | |
| 100 | void hudson_enable(device_t dev) |
| 101 | { |
| 102 | printk(BIOS_DEBUG, "sb800_enable()\n"); |
| 103 | } |
| 104 | |
| 105 | struct cbmem_entry *get_cbmem_toc(void) |
| 106 | { |
| 107 | uint32_t xdata = 0; |
| 108 | int xnvram_pos = 0xf8, xi; |
| 109 | for (xi = 0; xi<4; xi++) { |
| 110 | outb(xnvram_pos, BIOSRAM_INDEX); |
| 111 | xdata &= ~(0xff << (xi * 8)); |
| 112 | xdata |= inb(BIOSRAM_DATA) << (xi *8); |
| 113 | xnvram_pos++; |
| 114 | } |
| 115 | return (struct cbmem_entry *) xdata; |
| 116 | } |
| 117 | |
| 118 | |
| 119 | struct chip_operations southbridge_amd_agesa_hudson_ops = { |
| 120 | CHIP_NAME("ATI HUDSON") |
| 121 | .enable_dev = hudson_enable, |
| 122 | }; |