Rex Chou | d97d860 | 2023-07-20 14:00:24 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
| 6 | #include <soc/gpio.h> |
| 7 | |
| 8 | /* Pad configuration in ramstage */ |
| 9 | static const struct pad_config override_gpio_table[] = { |
| 10 | /* A21 : GPP_A21 ==> NC */ |
| 11 | PAD_NC(GPP_A21, NONE), |
| 12 | /* A21 : GPP_A22 ==> NC */ |
| 13 | PAD_NC(GPP_A22, NONE), |
Rex Chou | 24502f4 | 2023-10-06 13:25:02 +0800 | [diff] [blame^] | 14 | /* B5 : GPP_B5 ==> NC */ |
| 15 | PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), |
| 16 | /* B6 : GPP_B6 ==> NC */ |
| 17 | PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), |
Rex Chou | d97d860 | 2023-07-20 14:00:24 +0800 | [diff] [blame] | 18 | /* D3 : ISH_GP3 ==> NC */ |
| 19 | PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), |
| 20 | /* D8 : SRCCLKREQ3# ==> NC */ |
| 21 | PAD_NC(GPP_D8, NONE), |
| 22 | /* D15 : ISH_UART0_RTS# ==> NC */ |
| 23 | PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), |
| 24 | /* D16 : ISH_UART0_CTS# ==> NC */ |
| 25 | PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), |
| 26 | /* F6 : CNV_PA_BLANKING ==> NC */ |
| 27 | PAD_NC(GPP_F6, NONE), |
| 28 | /* F13 : SOC_PEN_DETECT_R_ODL ==> NC */ |
| 29 | PAD_NC(GPP_F13, NONE), |
| 30 | /* F15 : SOC_PEN_DETECT_ODL ==> NC */ |
| 31 | PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), |
| 32 | /* H8 : CNV_MFUART2_RXD ==> NC */ |
| 33 | PAD_NC(GPP_H8, NONE), |
| 34 | /* H9 : CNV_MFUART2_TXD ==> NC */ |
| 35 | PAD_NC(GPP_H9, NONE), |
| 36 | /* H12 : UART0_RTS# ==> NC */ |
| 37 | PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), |
| 38 | /* H13 : UART0_CTS# ==> NC */ |
| 39 | PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), |
Rex Chou | d97d860 | 2023-07-20 14:00:24 +0800 | [diff] [blame] | 40 | /* H22 : IMGCLKOUT3 ==> NC */ |
| 41 | PAD_NC(GPP_H22, NONE), |
| 42 | /* R6 : DMIC_CLK_A_1A ==> NC */ |
| 43 | PAD_NC(GPP_R6, NONE), |
| 44 | /* R7 : DMIC_DATA_1A ==> NC */ |
| 45 | PAD_NC(GPP_R7, NONE), |
| 46 | }; |
| 47 | |
| 48 | /* Early pad configuration in bootblock */ |
| 49 | static const struct pad_config early_gpio_table[] = { |
| 50 | /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ |
| 51 | PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), |
| 52 | /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ |
| 53 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), |
| 54 | /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ |
| 55 | PAD_CFG_GPI(GPP_F18, NONE, DEEP), |
| 56 | /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ |
| 57 | PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), |
| 58 | /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ |
| 59 | PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), |
| 60 | /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ |
| 61 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 62 | /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ |
| 63 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
| 64 | }; |
| 65 | |
| 66 | const struct pad_config *variant_gpio_override_table(size_t *num) |
| 67 | { |
| 68 | *num = ARRAY_SIZE(override_gpio_table); |
| 69 | return override_gpio_table; |
| 70 | } |
| 71 | |
| 72 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 73 | { |
| 74 | *num = ARRAY_SIZE(early_gpio_table); |
| 75 | return early_gpio_table; |
| 76 | } |