Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ |
| 4 | #define _SOC_TIGERLAKE_GPIO_DEFS_H_ |
| 5 | |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 6 | #include <soc/gpio_soc_defs.h> |
| 7 | |
| 8 | #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ |
| 9 | |
| 10 | #define NUM_GPIO_COMx_GPI_REGS(n) \ |
| 11 | (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) |
| 12 | |
| 13 | #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) |
| 14 | #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) |
| 15 | #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) |
| 16 | #define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) |
| 17 | #define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) |
| 18 | |
| 19 | #define NUM_GPI_STATUS_REGS \ |
| 20 | ((NUM_GPIO_COM0_GPI_REGS) +\ |
| 21 | (NUM_GPIO_COM1_GPI_REGS) +\ |
| 22 | (NUM_GPIO_COM2_GPI_REGS) +\ |
| 23 | (NUM_GPIO_COM4_GPI_REGS) +\ |
| 24 | (NUM_GPIO_COM5_GPI_REGS)) |
| 25 | /* |
| 26 | * IOxAPIC IRQs for the GPIOs |
| 27 | */ |
| 28 | |
| 29 | /* Group B */ |
| 30 | #define GPP_B0_IRQ 0x18 |
| 31 | #define GPP_B1_IRQ 0x19 |
| 32 | #define GPP_B2_IRQ 0x1A |
| 33 | #define GPP_B3_IRQ 0x1B |
| 34 | #define GPP_B4_IRQ 0x1C |
| 35 | #define GPP_B5_IRQ 0x1D |
| 36 | #define GPP_B6_IRQ 0x1E |
| 37 | #define GPP_B7_IRQ 0x1F |
| 38 | #define GPP_B8_IRQ 0x20 |
| 39 | #define GPP_B9_IRQ 0x21 |
| 40 | #define GPP_B10_IRQ 0x22 |
| 41 | #define GPP_B11_IRQ 0x23 |
| 42 | #define GPP_B12_IRQ 0x24 |
| 43 | #define GPP_B13_IRQ 0x25 |
| 44 | #define GPP_B14_IRQ 0x26 |
| 45 | #define GPP_B15_IRQ 0x27 |
| 46 | #define GPP_B16_IRQ 0x28 |
| 47 | #define GPP_B17_IRQ 0x29 |
| 48 | #define GPP_B18_IRQ 0x2A |
| 49 | #define GPP_B19_IRQ 0x2B |
| 50 | #define GPP_B20_IRQ 0x2C |
| 51 | #define GPP_B21_IRQ 0x2D |
| 52 | #define GPP_B22_IRQ 0x2E |
| 53 | #define GPP_B23_IRQ 0x2F |
| 54 | |
| 55 | /* Group T */ |
| 56 | #define GPP_T0_IRQ 0x30 |
| 57 | #define GPP_T1_IRQ 0x31 |
| 58 | #define GPP_T2_IRQ 0x32 |
| 59 | #define GPP_T3_IRQ 0x33 |
| 60 | #define GPP_T4_IRQ 0x34 |
| 61 | #define GPP_T5_IRQ 0x35 |
| 62 | #define GPP_T6_IRQ 0x36 |
| 63 | #define GPP_T7_IRQ 0x37 |
| 64 | #define GPP_T8_IRQ 0x38 |
| 65 | #define GPP_T9_IRQ 0x39 |
| 66 | #define GPP_T10_IRQ 0x3A |
| 67 | #define GPP_T11IRQ 0x3B |
| 68 | #define GPP_T12_IRQ 0x3C |
| 69 | #define GPP_T13_IRQ 0x3D |
| 70 | #define GPP_T14_IRQ 0x3E |
| 71 | #define GPP_T15_IRQ 0x3F |
| 72 | |
| 73 | /* Group A */ |
| 74 | #define GPP_A0_IRQ 0x40 |
| 75 | #define GPP_A1_IRQ 0x41 |
| 76 | #define GPP_A2_IRQ 0x42 |
| 77 | #define GPP_A3_IRQ 0x43 |
| 78 | #define GPP_A4_IRQ 0x44 |
| 79 | #define GPP_A5_IRQ 0x45 |
| 80 | #define GPP_A6_IRQ 0x46 |
| 81 | #define GPP_A7_IRQ 0x47 |
| 82 | #define GPP_A8_IRQ 0x48 |
| 83 | #define GPP_A9_IRQ 0x49 |
| 84 | #define GPP_A10_IRQ 0x4A |
| 85 | #define GPP_A11_IRQ 0x4B |
| 86 | #define GPP_A12_IRQ 0x4C |
| 87 | #define GPP_A13_IRQ 0x4D |
| 88 | #define GPP_A14_IRQ 0x4E |
| 89 | #define GPP_A15_IRQ 0x4F |
| 90 | #define GPP_A16_IRQ 0x50 |
| 91 | #define GPP_A17_IRQ 0x51 |
| 92 | #define GPP_A18_IRQ 0x52 |
| 93 | #define GPP_A19_IRQ 0x53 |
| 94 | #define GPP_A20_IRQ 0x54 |
| 95 | #define GPP_A21_IRQ 0x55 |
| 96 | #define GPP_A22_IRQ 0x56 |
| 97 | #define GPP_A23_IRQ 0x57 |
| 98 | |
| 99 | /* Group R */ |
| 100 | #define GPP_R0_IRQ 0x58 |
| 101 | #define GPP_R1_IRQ 0x59 |
| 102 | #define GPP_R2_IRQ 0x5A |
| 103 | #define GPP_R3_IRQ 0x5B |
| 104 | #define GPP_R4_IRQ 0x5C |
| 105 | #define GPP_R5_IRQ 0x5D |
| 106 | #define GPP_R6_IRQ 0x5E |
| 107 | #define GPP_R7_IRQ 0x5F |
| 108 | |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 109 | /* Group D */ |
| 110 | #define GPD0_IRQ 0x60 |
| 111 | #define GPD1_IRQ 0x61 |
| 112 | #define GPD2_IRQ 0x62 |
| 113 | #define GPD3_IRQ 0x63 |
| 114 | #define GPD4_IRQ 0x64 |
| 115 | #define GPD5_IRQ 0x65 |
| 116 | #define GPD6_IRQ 0x66 |
| 117 | #define GPD7_IRQ 0x67 |
| 118 | #define GPD8_IRQ 0x68 |
| 119 | #define GPD9_IRQ 0x69 |
| 120 | #define GPD10_IRQ 0x6A |
| 121 | #define GPD11_IRQ 0x6B |
| 122 | |
| 123 | /* Group S */ |
| 124 | #define GPP_S0_IRQ 0x6C |
| 125 | #define GPP_S1_IRQ 0x6D |
| 126 | #define GPP_S2_IRQ 0x6E |
| 127 | #define GPP_S3_IRQ 0x6F |
| 128 | #define GPP_S4_IRQ 0x70 |
| 129 | #define GPP_S5_IRQ 0x71 |
| 130 | #define GPP_S6_IRQ 0x72 |
| 131 | #define GPP_S7_IRQ 0x73 |
| 132 | |
| 133 | /* Group H */ |
| 134 | #define GPP_H0_IRQ 0x74 |
| 135 | #define GPP_H1_IRQ 0x75 |
| 136 | #define GPP_H2_IRQ 0x76 |
| 137 | #define GPP_H3_IRQ 0x77 |
| 138 | #define GPP_H4_IRQ 0x18 |
| 139 | #define GPP_H5_IRQ 0x19 |
| 140 | #define GPP_H6_IRQ 0x1A |
| 141 | #define GPP_H7_IRQ 0x1B |
| 142 | #define GPP_H8_IRQ 0x1C |
| 143 | #define GPP_H9_IRQ 0x1D |
| 144 | #define GPP_H10_IRQ 0x1E |
| 145 | #define GPP_H11_IRQ 0x1F |
| 146 | #define GPP_H12_IRQ 0x20 |
| 147 | #define GPP_H13_IRQ 0x21 |
| 148 | #define GPP_H14_IRQ 0x22 |
| 149 | #define GPP_H15_IRQ 0x23 |
| 150 | #define GPP_H16_IRQ 0x24 |
| 151 | #define GPP_H17_IRQ 0x25 |
| 152 | #define GPP_H18_IRQ 0x26 |
| 153 | #define GPP_H19_IRQ 0x27 |
| 154 | #define GPP_H20_IRQ 0x28 |
| 155 | #define GPP_H21_IRQ 0x29 |
| 156 | #define GPP_H22_IRQ 0x2A |
| 157 | #define GPP_H23_IRQ 0x2B |
| 158 | |
| 159 | /* Group D */ |
| 160 | #define GPP_D0_IRQ 0x2C |
| 161 | #define GPP_D1_IRQ 0x2D |
| 162 | #define GPP_D2_IRQ 0x2E |
| 163 | #define GPP_D3_IRQ 0x2F |
| 164 | #define GPP_D4_IRQ 0x30 |
| 165 | #define GPP_D5_IRQ 0x31 |
| 166 | #define GPP_D6_IRQ 0x32 |
| 167 | #define GPP_D7_IRQ 0x33 |
| 168 | #define GPP_D8_IRQ 0x34 |
| 169 | #define GPP_D9_IRQ 0x35 |
| 170 | #define GPP_D10_IRQ 0x36 |
| 171 | #define GPP_D11_IRQ 0x37 |
| 172 | #define GPP_D12_IRQ 0x38 |
| 173 | #define GPP_D13_IRQ 0x39 |
| 174 | #define GPP_D14_IRQ 0x3A |
| 175 | #define GPP_D15_IRQ 0x3B |
| 176 | #define GPP_D16_IRQ 0x3C |
| 177 | #define GPP_D17_IRQ 0x3D |
| 178 | #define GPP_D18_IRQ 0x3E |
| 179 | #define GPP_D19_IRQ 0x3F |
| 180 | |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 181 | /* Group U */ |
| 182 | #define GPP_U0_IRQ 0x40 |
| 183 | #define GPP_U1IRQ 0x41 |
| 184 | #define GPP_U2_IRQ 0x42 |
| 185 | #define GPP_U3_IRQ 0x43 |
| 186 | #define GPP_U4_IRQ 0x44 |
| 187 | #define GPP_U5_IRQ 0x45 |
| 188 | #define GPP_U6_IRQ 0x46 |
| 189 | #define GPP_U7_IRQ 0x47 |
| 190 | #define GPP_U8_IRQ 0x48 |
| 191 | #define GPP_U9_IRQ 0x49 |
| 192 | #define GPP_U10_IRQ 0x4A |
| 193 | #define GPP_U11_IRQ 0x4B |
| 194 | #define GPP_U12_IRQ 0x4C |
| 195 | #define GPP_U13_IRQ 0x4D |
| 196 | #define GPP_U14_IRQ 0x4E |
| 197 | #define GPP_U15_IRQ 0x4F |
| 198 | #define GPP_U16_IRQ 0x50 |
| 199 | #define GPP_U17_IRQ 0x51 |
| 200 | #define GPP_U18_IRQ 0x52 |
| 201 | #define GPP_U19_IRQ 0x53 |
| 202 | |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 203 | #define GPP_VGPIO4_IRQ 0x54 |
| 204 | |
| 205 | /* Group F */ |
| 206 | #define GPP_F0_IRQ 0x56 |
| 207 | #define GPP_F1_IRQ 0x57 |
| 208 | #define GPP_F2_IRQ 0x58 |
| 209 | #define GPP_F3_IRQ 0x59 |
| 210 | #define GPP_F4_IRQ 0x5A |
| 211 | #define GPP_F5_IRQ 0x5B |
| 212 | #define GPP_F6_IRQ 0x5C |
| 213 | #define GPP_F7_IRQ 0x5D |
| 214 | #define GPP_F8_IRQ 0x5E |
| 215 | #define GPP_F9_IRQ 0x5F |
| 216 | #define GPP_F10_IRQ 0x60 |
| 217 | #define GPP_F11_IRQ 0x61 |
| 218 | #define GPP_F12_IRQ 0x62 |
| 219 | #define GPP_F13_IRQ 0x63 |
| 220 | #define GPP_F14_IRQ 0x64 |
| 221 | #define GPP_F15_IRQ 0x65 |
| 222 | #define GPP_F16_IRQ 0x66 |
| 223 | #define GPP_F17_IRQ 0x67 |
| 224 | #define GPP_F18_IRQ 0x68 |
| 225 | #define GPP_F19_IRQ 0x69 |
| 226 | #define GPP_F20_IRQ 0x6A |
| 227 | #define GPP_F21_IRQ 0x6B |
| 228 | #define GPP_F22_IRQ 0x6C |
| 229 | #define GPP_F23_IRQ 0x6D |
| 230 | |
| 231 | /* Group C */ |
Jakub Czapiga | b911c48 | 2023-01-11 11:50:33 +0100 | [diff] [blame] | 232 | #define GPP_C0_IRQ 0x6E |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 233 | #define GPP_C1_IRQ 0x6F |
| 234 | #define GPP_C2_IRQ 0x70 |
| 235 | #define GPP_C3_IRQ 0x71 |
| 236 | #define GPP_C4_IRQ 0x72 |
| 237 | #define GPP_C5_IRQ 0x73 |
| 238 | #define GPP_C6_IRQ 0x74 |
| 239 | #define GPP_C7_IRQ 0x75 |
| 240 | #define GPP_C8_IRQ 0x76 |
| 241 | #define GPP_C9_IRQ 0x77 |
| 242 | #define GPP_C10_IRQ 0x18 |
| 243 | #define GPP_C11_IRQ 0x19 |
| 244 | #define GPP_C12_IRQ 0x1A |
| 245 | #define GPP_C13_IRQ 0x1B |
| 246 | #define GPP_C14_IRQ 0x1C |
| 247 | #define GPP_C15_IRQ 0x1D |
| 248 | #define GPP_C16_IRQ 0x1E |
| 249 | #define GPP_C17_IRQ 0x1F |
| 250 | #define GPP_C18_IRQ 0x20 |
| 251 | #define GPP_C19_IRQ 0x21 |
| 252 | #define GPP_C20_IRQ 0x22 |
| 253 | #define GPP_C21_IRQ 0x23 |
| 254 | #define GPP_C22_IRQ 0x24 |
| 255 | #define GPP_C23_IRQ 0x25 |
| 256 | |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 257 | /* Group E */ |
| 258 | #define GPP_E0_IRQ 0x26 |
| 259 | #define GPP_E1_IRQ 0x27 |
| 260 | #define GPP_E2_IRQ 0x28 |
| 261 | #define GPP_E3_IRQ 0x29 |
| 262 | #define GPP_E4_IRQ 0x30 |
| 263 | #define GPP_E5_IRQ 0x31 |
| 264 | #define GPP_E6_IRQ 0x32 |
| 265 | #define GPP_E7_IRQ 0x33 |
| 266 | #define GPP_E8_IRQ 0x34 |
| 267 | #define GPP_E9_IRQ 0x35 |
| 268 | #define GPP_E10_IRQ 0x36 |
| 269 | #define GPP_E11_IRQ 0x37 |
| 270 | #define GPP_E12_IRQ 0x38 |
| 271 | #define GPP_E13_IRQ 0x39 |
| 272 | #define GPP_E14_IRQ 0x3A |
| 273 | #define GPP_E15_IRQ 0x3B |
| 274 | #define GPP_E16_IRQ 0x3C |
| 275 | #define GPP_E17_IRQ 0x3D |
| 276 | #define GPP_E18_IRQ 0x3E |
| 277 | #define GPP_E19_IRQ 0x3F |
| 278 | #define GPP_E20_IRQ 0x40 |
| 279 | #define GPP_E21_IRQ 0x41 |
| 280 | #define GPP_E22_IRQ 0x42 |
| 281 | #define GPP_E23_IRQ 0x43 |
| 282 | |
| 283 | /* Register defines. */ |
| 284 | #define GPIO_MISCCFG 0x10 |
| 285 | #define GPE_DW_SHIFT 8 |
| 286 | #define GPE_DW_MASK 0xfff00 |
| 287 | #define HOSTSW_OWN_REG_0 0xb0 |
| 288 | #define GPI_INT_STS_0 0x100 |
Michael Niewöhner | 9abeb9c | 2021-09-15 16:40:35 +0200 | [diff] [blame] | 289 | #define GPI_INT_EN_0 0x120 |
Maulik V Vaghela | afe8409 | 2022-05-06 10:27:50 +0530 | [diff] [blame] | 290 | #define GPI_GPE_STS_0 0x140 |
| 291 | #define GPI_GPE_EN_0 0x160 |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 292 | #define GPI_SMI_STS_0 0x180 |
| 293 | #define GPI_SMI_EN_0 0x1A0 |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 294 | #define GPI_NMI_STS_0 0x1c0 |
| 295 | #define GPI_NMI_EN_0 0x1e0 |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 296 | #define PAD_CFG_BASE 0x700 |
| 297 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 298 | #endif |