Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
Tim Wawrzynczak | 654d9d6 | 2020-03-19 13:56:21 -0600 | [diff] [blame] | 6 | |
| 7 | # GPE configuration |
| 8 | # Note that GPE events called out in ASL code rely on this |
| 9 | # route. i.e. If this route changes then the affected GPE |
| 10 | # offset bits also need to be changed. |
| 11 | |
| 12 | # TODO: Figure out GPE DW1&2 |
| 13 | register "pmc_gpe0_dw0" = "GPP_C" |
| 14 | #register "pmc_gpe0_dw1" = "??" |
| 15 | #register "pmc_gpe0_dw2" = "??" |
| 16 | |
| 17 | # Wilco EC host command ranges |
| 18 | register "gen1_dec" = "0x00040931" # 0x930-0x937 |
| 19 | register "gen2_dec" = "0x00040941" # 0x940-0x947 |
| 20 | register "gen3_dec" = "0x000c0951" # 0x950-0x95f |
| 21 | |
| 22 | register "s0ix_enable" = "1" |
| 23 | |
| 24 | # TODO: not yet |
| 25 | register "dptf_enable" = "0" |
| 26 | |
| 27 | register "tcc_offset" = "0" |
| 28 | |
| 29 | # FSP configuration |
| 30 | register "SaGv" = "SaGv_Disabled" |
| 31 | |
| 32 | register "SataEnable" = "1" |
| 33 | register "SataMode" = "0" |
| 34 | register "SataSalpSupport" = "1" |
| 35 | register "SmbusEnable" = "1" |
| 36 | |
| 37 | # TODO: the lengths are all MID for right now. |
| 38 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 |
| 39 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 2 |
| 40 | register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Ext USB Port 1 (Right) |
| 41 | register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Ext USB Port 2 (Left) |
| 42 | register "usb2_ports[4]" = "USB2_PORT_EMPTY" |
| 43 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera |
| 44 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 3042 (WWAN) |
| 45 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH |
| 46 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" |
| 47 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT |
| 48 | |
| 49 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 |
| 50 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 |
| 51 | |
| 52 | # PCIe root port 6 (WLAN), clock 1 |
| 53 | register "PcieRpEnable[5]" = "1" |
| 54 | register "PcieClkSrcUsage[1]" = "5" |
| 55 | register "PcieClkSrcClkReq[1]" = "1" |
| 56 | |
| 57 | # PCIe root port 7 (Card Reader), clock 4 |
| 58 | register "PcieRpEnable[6]" = "1" |
| 59 | register "PcieClkSrcUsage[4]" = "6" |
| 60 | register "PcieClkSrcClkReq[4]" = "4" |
| 61 | |
Tim Wawrzynczak | 654d9d6 | 2020-03-19 13:56:21 -0600 | [diff] [blame] | 62 | # PCIe root port 9 (NVMe), clock 2 |
| 63 | register "PcieRpEnable[8]" = "1" |
| 64 | register "PcieClkSrcUsage[2]" = "8" |
| 65 | register "PcieClkSrcClkReq[2]" = "2" |
| 66 | |
| 67 | # Mark unused SRCCLKREQs as so |
| 68 | register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" |
| 69 | register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" |
| 70 | register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" |
| 71 | |
| 72 | # Intel Common SoC Config |
| 73 | #+-------------------+---------------------------+ |
| 74 | #| Field | Value | |
| 75 | #+-------------------+---------------------------+ |
| 76 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 77 | #| I2C0 | Touchscreen | |
| 78 | #| I2C1 | Touchpad | |
| 79 | #| I2C2 | ISH ? | |
| 80 | #| I2C3 | cr50 TPM | |
| 81 | #| I2C5 | ISH ? | |
| 82 | #+-------------------+---------------------------+ |
| 83 | register "common_soc_config" = "{ |
| 84 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 85 | .i2c[0] = { |
| 86 | .speed = I2C_SPEED_FAST, |
| 87 | }, |
| 88 | .i2c[1] = { |
| 89 | .speed = I2C_SPEED_FAST, |
| 90 | }, |
| 91 | .i2c[2] = { |
| 92 | .speed = I2C_SPEED_FAST, |
| 93 | }, |
| 94 | .i2c[3] = { |
| 95 | .speed = I2C_SPEED_FAST, |
| 96 | .early_init = 1, |
| 97 | }, |
| 98 | .i2c[5] = { |
| 99 | .speed = I2C_SPEED_FAST, |
| 100 | }, |
| 101 | }" |
| 102 | |
| 103 | register "SerialIoI2cMode" = "{ |
| 104 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 105 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 106 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 107 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 108 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 109 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 110 | }" |
| 111 | |
| 112 | register "SerialIoUartMode" = "{ |
| 113 | [PchSerialIoIndexUART0] = PchSerialIoDisabled, |
| 114 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 115 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 116 | }" |
| 117 | |
| 118 | register "SerialIoGSpiMode" = "{ |
| 119 | [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
| 120 | [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| 121 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 122 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 123 | }" |
| 124 | |
| 125 | # HD Audio |
| 126 | register "PchHdaDspEnable" = "1" |
| 127 | register "PchHdaAudioLinkHdaEnable" = "0" |
| 128 | register "PchHdaAudioLinkDmicEnable[0]" = "1" |
| 129 | register "PchHdaAudioLinkDmicEnable[1]" = "1" |
| 130 | register "PchHdaAudioLinkSspEnable[0]" = "1" |
| 131 | register "PchHdaAudioLinkSspEnable[1]" = "1" |
| 132 | |
| 133 | # TCSS USB3 |
| 134 | register "TcssXhciEn" = "1" |
| 135 | |
| 136 | # DisplayPort |
| 137 | register "DdiPortAConfig" = "1" # eDP |
| 138 | register "DdiPortAHpd" = "1" |
| 139 | |
| 140 | # Disable PM to allow for shorter irq pulses |
| 141 | register "gpio_override_pm" = "1" |
| 142 | register "gpio_pm[0]" = "0" |
| 143 | register "gpio_pm[1]" = "0" |
| 144 | register "gpio_pm[2]" = "0" |
| 145 | register "gpio_pm[3]" = "0" |
| 146 | register "gpio_pm[4]" = "0" |
| 147 | |
| 148 | # Enable "Intel Speed Shift Technology" |
| 149 | register "speed_shift_enable" = "1" |
| 150 | |
| 151 | device domain 0 on |
| 152 | device pci 00.0 on end # Host Bridge |
| 153 | device pci 02.0 on end # Graphics |
| 154 | device pci 04.0 on end # DPTF |
| 155 | device pci 05.0 off end # IPU |
| 156 | device pci 06.0 off end # PEG60 |
| 157 | device pci 07.0 on end # TBT_PCIe0 |
| 158 | device pci 07.1 on end # TBT_PCIe0 |
| 159 | device pci 07.2 on end # TBT_PCIe0 |
| 160 | device pci 07.3 on end # TBT_PCIe0 |
| 161 | device pci 08.0 on end # GNA |
| 162 | device pci 09.0 off end # NPK |
| 163 | device pci 0a.0 off end # Crash-log SRAM |
| 164 | device pci 0d.0 on end # USB xHCI |
| 165 | device pci 0d.1 off end # USB xDCI |
| 166 | device pci 0d.2 off end # TBT DMA0 |
| 167 | device pci 0d.3 off end # TBT DMA1 |
| 168 | device pci 0e.0 off end # VMD |
| 169 | |
| 170 | device pci 10.0 off end # THC #0 |
| 171 | device pci 10.1 off end # THC #1 |
| 172 | device pci 10.2 on end # CNVi Bluetooth |
| 173 | device pci 11.0 off end # UART #3 |
| 174 | device pci 11.1 off end # UART4 |
| 175 | device pci 11.2 off end # UART5 |
| 176 | device pci 11.3 off end # UART6 |
| 177 | |
| 178 | device pci 12.0 on end # ISH |
| 179 | device pci 12.6 off end # GSPI #2 |
| 180 | device pci 13.0 off end # GSPI #3 |
| 181 | device pci 13.1 off end # GSPI #4 |
| 182 | device pci 13.2 off end # GSPI #5 |
| 183 | device pci 13.3 off end # GSPI #6 |
| 184 | |
| 185 | device pci 14.0 on |
| 186 | chip drivers/usb/acpi |
| 187 | register "desc" = ""Root Hub"" |
| 188 | register "type" = "UPC_TYPE_HUB" |
| 189 | device usb 0.0 on |
| 190 | chip drivers/usb/acpi |
| 191 | register "desc" = ""Type-C Port 1"" |
| 192 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 193 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 194 | device usb 2.0 on end |
| 195 | end |
| 196 | chip drivers/usb/acpi |
| 197 | register "desc" = ""Type-C Port 2"" |
| 198 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 199 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 200 | device usb 2.1 on end |
| 201 | end |
| 202 | chip drivers/usb/acpi |
| 203 | register "desc" = ""Type-A Port 1 (Right)"" |
| 204 | register "type" = "UPC_TYPE_USB3_A" |
| 205 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 206 | device usb 2.2 on end |
| 207 | end |
| 208 | chip drivers/usb/acpi |
| 209 | register "desc" = ""Type-A Port 2 (Left)"" |
| 210 | register "type" = "UPC_TYPE_USB3_A" |
| 211 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 212 | device usb 2.3 on end |
| 213 | end |
| 214 | chip drivers/usb/acpi |
| 215 | register "desc" = ""Camera"" |
| 216 | register "type" = "UPC_TYPE_INTERNAL" |
| 217 | device usb 2.5 on end |
| 218 | end |
| 219 | chip drivers/usb/acpi |
| 220 | register "desc" = ""M.2 3042 (WWAN)"" |
| 221 | register "type" = "UPC_TYPE_INTERNAL" |
| 222 | device usb 2.6 on end |
| 223 | end |
| 224 | chip drivers/usb/acpi |
| 225 | register "desc" = ""USH"" |
| 226 | register "type" = "UPC_TYPE_INTERNAL" |
| 227 | device usb 2.7 on end |
| 228 | end |
| 229 | chip drivers/usb/acpi |
| 230 | register "desc" = ""M.2 2230 (BT)"" |
| 231 | register "type" = "UPC_TYPE_INTERNAL" |
| 232 | device usb 2.9 on end |
| 233 | end |
| 234 | chip drivers/usb/acpi |
| 235 | register "desc" = ""Type-C Port 1"" |
| 236 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 237 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 238 | device usb 3.0 on end |
| 239 | end |
| 240 | chip drivers/usb/acpi |
| 241 | register "desc" = ""Type-C Port 2"" |
| 242 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 243 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 244 | device usb 3.1 on end |
| 245 | end |
| 246 | chip drivers/usb/acpi |
| 247 | register "desc" = ""Type-A Port 1 (Right)"" |
| 248 | register "type" = "UPC_TYPE_USB3_A" |
| 249 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 250 | device usb 3.2 on end |
| 251 | end |
| 252 | chip drivers/usb/acpi |
| 253 | register "desc" = ""Type-A Port 2 (Left)"" |
| 254 | register "type" = "UPC_TYPE_USB3_A" |
| 255 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 256 | device usb 3.3 on end |
| 257 | end |
| 258 | chip drivers/usb/acpi |
| 259 | register "desc" = ""WWAN"" |
| 260 | register "type" = "UPC_TYPE_INTERNAL" |
| 261 | device usb 3.4 on end |
| 262 | end |
| 263 | end |
| 264 | end |
| 265 | end # USB 3.2 2x1 xHCI HC |
| 266 | |
| 267 | device pci 14.1 off end # USB 3.2 1x1 xDCI HC |
| 268 | device pci 14.2 on end # Shared SRAM |
| 269 | |
| 270 | chip drivers/intel/wifi |
| 271 | register "wake" = "GPE0_PME_B0" |
| 272 | device pci 14.3 on end # CNVi WiFi |
| 273 | end |
| 274 | |
| 275 | device pci 15.0 on end # I2C #0 |
| 276 | device pci 15.1 on end # I2C #1 |
| 277 | device pci 15.2 on end # I2C #2 |
| 278 | device pci 15.3 on |
| 279 | chip drivers/i2c/tpm |
| 280 | register "hid" = ""GOOG0005"" |
| 281 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" |
| 282 | device i2c 50 on end |
| 283 | end |
| 284 | end # I2C #3 |
| 285 | |
| 286 | device pci 16.0 on end # HECI #1 |
| 287 | device pci 16.1 off end # HECI #2 |
| 288 | device pci 16.2 off end # IDE-R |
| 289 | device pci 16.3 off end # KT-T |
| 290 | device pci 16.4 on end # HECI #3 |
| 291 | device pci 16.5 on end # HECI #4 |
| 292 | device pci 17.0 on end # SATA (AHCI) |
| 293 | device pci 19.0 off end # I2C #4 |
| 294 | device pci 19.1 on end # I2C #5 |
| 295 | device pci 19.2 on end # UART #2 |
| 296 | |
| 297 | device pci 1c.0 on end # PCIe Root Port #1 (USB) |
| 298 | device pci 1c.1 on end # PCIe Root Port #2 (USB) |
| 299 | device pci 1c.2 off end # PCIe Root Port #3 () |
| 300 | device pci 1c.3 on end # PCIe Root Port #4 (WWAN) |
| 301 | device pci 1c.4 on end # PCIe Root Port #5 (LTE) |
| 302 | device pci 1c.5 on end # PCIe Root Port #6 (WiFi) |
| 303 | device pci 1c.6 on end # PCIe Root Port #7 (Card reader) |
| 304 | device pci 1c.7 on |
| 305 | chip drivers/net |
| 306 | register "wake" = "GPE0_PME_B0" |
| 307 | device pci 00.0 on end |
| 308 | end |
| 309 | end # PCIe Root Port #8 (LAN) |
| 310 | device pci 1d.0 on end # PCIe Root Port #9 (NVMe) |
| 311 | device pci 1d.1 off end # PCIe Root Port #10 (NVMe) |
| 312 | device pci 1d.2 off end # PCIe Root Port #11 (NVMe) |
| 313 | device pci 1d.3 off end # PCIe Root Port #12 (NVMe) |
| 314 | |
| 315 | device pci 1e.0 off end # UART #0 |
| 316 | device pci 1e.1 off end # UART #1 |
| 317 | device pci 1e.2 off end # GSPI #0 |
| 318 | device pci 1e.3 off end # GSPI #1 |
| 319 | |
| 320 | device pci 1f.0 on |
| 321 | chip ec/google/wilco |
| 322 | device pnp 0c09.0 on end |
| 323 | end |
| 324 | end # eSPI |
| 325 | device pci 1f.1 off end # P2SB |
| 326 | device pci 1f.2 on end # PMC |
| 327 | device pci 1f.3 on end # Intel HDA |
| 328 | device pci 1f.4 on end # SMBus |
| 329 | device pci 1f.5 on end # PCH SPI Flash Controller |
Varun Joshi | 2255eba | 2020-03-31 18:02:33 -0700 | [diff] [blame^] | 330 | device pci 1f.6 off end # GbE Controller |
Tim Wawrzynczak | 654d9d6 | 2020-03-19 13:56:21 -0600 | [diff] [blame] | 331 | device pci 1f.7 off end # Intel Trace Hub |
| 332 | end |
Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 333 | end |