Subrata Banik | 20fe24b | 2021-12-09 02:46:38 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | Support for PCI 2.2 standard. |
| 3 | |
| 4 | This file includes the definitions in the following specifications, |
| 5 | PCI Local Bus Specification, 2.2 |
| 6 | PCI-to-PCI Bridge Architecture Specification, Revision 1.2 |
| 7 | PC Card Standard, 8.0 |
| 8 | PCI Power Management Interface Specification, Revision 1.2 |
| 9 | |
| 10 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> |
| 11 | Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR> |
| 12 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 13 | |
| 14 | **/ |
| 15 | |
| 16 | #ifndef _PCI22_H_ |
| 17 | #define _PCI22_H_ |
| 18 | |
| 19 | #define PCI_MAX_BUS 255 |
| 20 | #define PCI_MAX_DEVICE 31 |
| 21 | #define PCI_MAX_FUNC 7 |
| 22 | |
| 23 | #pragma pack(1) |
| 24 | |
| 25 | /// |
| 26 | /// Common header region in PCI Configuration Space |
| 27 | /// Section 6.1, PCI Local Bus Specification, 2.2 |
| 28 | /// |
| 29 | typedef struct { |
| 30 | UINT16 VendorId; |
| 31 | UINT16 DeviceId; |
| 32 | UINT16 Command; |
| 33 | UINT16 Status; |
| 34 | UINT8 RevisionID; |
| 35 | UINT8 ClassCode[3]; |
| 36 | UINT8 CacheLineSize; |
| 37 | UINT8 LatencyTimer; |
| 38 | UINT8 HeaderType; |
| 39 | UINT8 BIST; |
| 40 | } PCI_DEVICE_INDEPENDENT_REGION; |
| 41 | |
| 42 | /// |
| 43 | /// PCI Device header region in PCI Configuration Space |
| 44 | /// Section 6.1, PCI Local Bus Specification, 2.2 |
| 45 | /// |
| 46 | typedef struct { |
| 47 | UINT32 Bar[6]; |
| 48 | UINT32 CISPtr; |
| 49 | UINT16 SubsystemVendorID; |
| 50 | UINT16 SubsystemID; |
| 51 | UINT32 ExpansionRomBar; |
| 52 | UINT8 CapabilityPtr; |
| 53 | UINT8 Reserved1[3]; |
| 54 | UINT32 Reserved2; |
| 55 | UINT8 InterruptLine; |
| 56 | UINT8 InterruptPin; |
| 57 | UINT8 MinGnt; |
| 58 | UINT8 MaxLat; |
| 59 | } PCI_DEVICE_HEADER_TYPE_REGION; |
| 60 | |
| 61 | /// |
| 62 | /// PCI Device Configuration Space |
| 63 | /// Section 6.1, PCI Local Bus Specification, 2.2 |
| 64 | /// |
| 65 | typedef struct { |
| 66 | PCI_DEVICE_INDEPENDENT_REGION Hdr; |
| 67 | PCI_DEVICE_HEADER_TYPE_REGION Device; |
| 68 | } PCI_TYPE00; |
| 69 | |
| 70 | /// |
| 71 | /// PCI-PCI Bridge header region in PCI Configuration Space |
| 72 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2 |
| 73 | /// |
| 74 | typedef struct { |
| 75 | UINT32 Bar[2]; |
| 76 | UINT8 PrimaryBus; |
| 77 | UINT8 SecondaryBus; |
| 78 | UINT8 SubordinateBus; |
| 79 | UINT8 SecondaryLatencyTimer; |
| 80 | UINT8 IoBase; |
| 81 | UINT8 IoLimit; |
| 82 | UINT16 SecondaryStatus; |
| 83 | UINT16 MemoryBase; |
| 84 | UINT16 MemoryLimit; |
| 85 | UINT16 PrefetchableMemoryBase; |
| 86 | UINT16 PrefetchableMemoryLimit; |
| 87 | UINT32 PrefetchableBaseUpper32; |
| 88 | UINT32 PrefetchableLimitUpper32; |
| 89 | UINT16 IoBaseUpper16; |
| 90 | UINT16 IoLimitUpper16; |
| 91 | UINT8 CapabilityPtr; |
| 92 | UINT8 Reserved[3]; |
| 93 | UINT32 ExpansionRomBAR; |
| 94 | UINT8 InterruptLine; |
| 95 | UINT8 InterruptPin; |
| 96 | UINT16 BridgeControl; |
| 97 | } PCI_BRIDGE_CONTROL_REGISTER; |
| 98 | |
| 99 | /// |
| 100 | /// PCI-to-PCI Bridge Configuration Space |
| 101 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2 |
| 102 | /// |
| 103 | typedef struct { |
| 104 | PCI_DEVICE_INDEPENDENT_REGION Hdr; |
| 105 | PCI_BRIDGE_CONTROL_REGISTER Bridge; |
| 106 | } PCI_TYPE01; |
| 107 | |
| 108 | typedef union { |
| 109 | PCI_TYPE00 Device; |
| 110 | PCI_TYPE01 Bridge; |
| 111 | } PCI_TYPE_GENERIC; |
| 112 | |
| 113 | /// |
| 114 | /// CardBus Controller Configuration Space, |
| 115 | /// Section 4.5.1, PC Card Standard. 8.0 |
| 116 | /// |
| 117 | typedef struct { |
| 118 | UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base |
| 119 | UINT8 Cap_Ptr; |
| 120 | UINT8 Reserved; |
| 121 | UINT16 SecondaryStatus; ///< Secondary Status |
| 122 | UINT8 PciBusNumber; ///< PCI Bus Number |
| 123 | UINT8 CardBusBusNumber; ///< CardBus Bus Number |
| 124 | UINT8 SubordinateBusNumber; ///< Subordinate Bus Number |
| 125 | UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer |
| 126 | UINT32 MemoryBase0; ///< Memory Base Register 0 |
| 127 | UINT32 MemoryLimit0; ///< Memory Limit Register 0 |
| 128 | UINT32 MemoryBase1; |
| 129 | UINT32 MemoryLimit1; |
| 130 | UINT32 IoBase0; |
| 131 | UINT32 IoLimit0; ///< I/O Base Register 0 |
| 132 | UINT32 IoBase1; ///< I/O Limit Register 0 |
| 133 | UINT32 IoLimit1; |
| 134 | UINT8 InterruptLine; ///< Interrupt Line |
| 135 | UINT8 InterruptPin; ///< Interrupt Pin |
| 136 | UINT16 BridgeControl; ///< Bridge Control |
| 137 | } PCI_CARDBUS_CONTROL_REGISTER; |
| 138 | |
| 139 | // |
| 140 | // Definitions of PCI class bytes and manipulation macros. |
| 141 | // |
| 142 | #define PCI_CLASS_OLD 0x00 |
| 143 | #define PCI_CLASS_OLD_OTHER 0x00 |
| 144 | #define PCI_CLASS_OLD_VGA 0x01 |
| 145 | |
| 146 | #define PCI_CLASS_MASS_STORAGE 0x01 |
| 147 | #define PCI_CLASS_MASS_STORAGE_SCSI 0x00 |
| 148 | #define PCI_CLASS_MASS_STORAGE_IDE 0x01 |
| 149 | #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02 |
| 150 | #define PCI_CLASS_MASS_STORAGE_IPI 0x03 |
| 151 | #define PCI_CLASS_MASS_STORAGE_RAID 0x04 |
| 152 | #define PCI_CLASS_MASS_STORAGE_OTHER 0x80 |
| 153 | |
| 154 | #define PCI_CLASS_NETWORK 0x02 |
| 155 | #define PCI_CLASS_NETWORK_ETHERNET 0x00 |
| 156 | #define PCI_CLASS_NETWORK_TOKENRING 0x01 |
| 157 | #define PCI_CLASS_NETWORK_FDDI 0x02 |
| 158 | #define PCI_CLASS_NETWORK_ATM 0x03 |
| 159 | #define PCI_CLASS_NETWORK_ISDN 0x04 |
| 160 | #define PCI_CLASS_NETWORK_OTHER 0x80 |
| 161 | |
| 162 | #define PCI_CLASS_DISPLAY 0x03 |
| 163 | #define PCI_CLASS_DISPLAY_VGA 0x00 |
| 164 | #define PCI_IF_VGA_VGA 0x00 |
| 165 | #define PCI_IF_VGA_8514 0x01 |
| 166 | #define PCI_CLASS_DISPLAY_XGA 0x01 |
| 167 | #define PCI_CLASS_DISPLAY_3D 0x02 |
| 168 | #define PCI_CLASS_DISPLAY_OTHER 0x80 |
| 169 | |
| 170 | #define PCI_CLASS_MEDIA 0x04 |
| 171 | #define PCI_CLASS_MEDIA_VIDEO 0x00 |
| 172 | #define PCI_CLASS_MEDIA_AUDIO 0x01 |
| 173 | #define PCI_CLASS_MEDIA_TELEPHONE 0x02 |
| 174 | #define PCI_CLASS_MEDIA_OTHER 0x80 |
| 175 | |
| 176 | #define PCI_CLASS_MEMORY_CONTROLLER 0x05 |
| 177 | #define PCI_CLASS_MEMORY_RAM 0x00 |
| 178 | #define PCI_CLASS_MEMORY_FLASH 0x01 |
| 179 | #define PCI_CLASS_MEMORY_OTHER 0x80 |
| 180 | |
| 181 | #define PCI_CLASS_BRIDGE 0x06 |
| 182 | #define PCI_CLASS_BRIDGE_HOST 0x00 |
| 183 | #define PCI_CLASS_BRIDGE_ISA 0x01 |
| 184 | #define PCI_CLASS_BRIDGE_EISA 0x02 |
| 185 | #define PCI_CLASS_BRIDGE_MCA 0x03 |
| 186 | #define PCI_CLASS_BRIDGE_P2P 0x04 |
| 187 | #define PCI_IF_BRIDGE_P2P 0x00 |
| 188 | #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01 |
| 189 | #define PCI_CLASS_BRIDGE_PCMCIA 0x05 |
| 190 | #define PCI_CLASS_BRIDGE_NUBUS 0x06 |
| 191 | #define PCI_CLASS_BRIDGE_CARDBUS 0x07 |
| 192 | #define PCI_CLASS_BRIDGE_RACEWAY 0x08 |
| 193 | #define PCI_CLASS_BRIDGE_OTHER 0x80 |
| 194 | #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80 |
| 195 | |
| 196 | #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers |
| 197 | #define PCI_SUBCLASS_SERIAL 0x00 |
| 198 | #define PCI_IF_GENERIC_XT 0x00 |
| 199 | #define PCI_IF_16450 0x01 |
| 200 | #define PCI_IF_16550 0x02 |
| 201 | #define PCI_IF_16650 0x03 |
| 202 | #define PCI_IF_16750 0x04 |
| 203 | #define PCI_IF_16850 0x05 |
| 204 | #define PCI_IF_16950 0x06 |
| 205 | #define PCI_SUBCLASS_PARALLEL 0x01 |
| 206 | #define PCI_IF_PARALLEL_PORT 0x00 |
| 207 | #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01 |
| 208 | #define PCI_IF_ECP_PARALLEL_PORT 0x02 |
| 209 | #define PCI_IF_1284_CONTROLLER 0x03 |
| 210 | #define PCI_IF_1284_DEVICE 0xFE |
| 211 | #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02 |
| 212 | #define PCI_SUBCLASS_MODEM 0x03 |
| 213 | #define PCI_IF_GENERIC_MODEM 0x00 |
| 214 | #define PCI_IF_16450_MODEM 0x01 |
| 215 | #define PCI_IF_16550_MODEM 0x02 |
| 216 | #define PCI_IF_16650_MODEM 0x03 |
| 217 | #define PCI_IF_16750_MODEM 0x04 |
| 218 | #define PCI_SUBCLASS_SCC_OTHER 0x80 |
| 219 | |
| 220 | #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08 |
| 221 | #define PCI_SUBCLASS_PIC 0x00 |
| 222 | #define PCI_IF_8259_PIC 0x00 |
| 223 | #define PCI_IF_ISA_PIC 0x01 |
| 224 | #define PCI_IF_EISA_PIC 0x02 |
| 225 | #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory. |
| 226 | #define PCI_IF_APIC_CONTROLLER2 0x20 |
| 227 | #define PCI_SUBCLASS_DMA 0x01 |
| 228 | #define PCI_IF_8237_DMA 0x00 |
| 229 | #define PCI_IF_ISA_DMA 0x01 |
| 230 | #define PCI_IF_EISA_DMA 0x02 |
| 231 | #define PCI_SUBCLASS_TIMER 0x02 |
| 232 | #define PCI_IF_8254_TIMER 0x00 |
| 233 | #define PCI_IF_ISA_TIMER 0x01 |
| 234 | #define PCI_IF_EISA_TIMER 0x02 |
| 235 | #define PCI_SUBCLASS_RTC 0x03 |
| 236 | #define PCI_IF_GENERIC_RTC 0x00 |
| 237 | #define PCI_IF_ISA_RTC 0x01 |
| 238 | #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller |
| 239 | #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80 |
| 240 | |
| 241 | #define PCI_CLASS_INPUT_DEVICE 0x09 |
| 242 | #define PCI_SUBCLASS_KEYBOARD 0x00 |
| 243 | #define PCI_SUBCLASS_PEN 0x01 |
| 244 | #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02 |
| 245 | #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03 |
| 246 | #define PCI_SUBCLASS_GAMEPORT 0x04 |
| 247 | #define PCI_IF_GAMEPORT 0x00 |
| 248 | #define PCI_IF_GAMEPORT1 0x10 |
| 249 | #define PCI_SUBCLASS_INPUT_OTHER 0x80 |
| 250 | |
| 251 | #define PCI_CLASS_DOCKING_STATION 0x0A |
| 252 | #define PCI_SUBCLASS_DOCKING_GENERIC 0x00 |
| 253 | #define PCI_SUBCLASS_DOCKING_OTHER 0x80 |
| 254 | |
| 255 | #define PCI_CLASS_PROCESSOR 0x0B |
| 256 | #define PCI_SUBCLASS_PROC_386 0x00 |
| 257 | #define PCI_SUBCLASS_PROC_486 0x01 |
| 258 | #define PCI_SUBCLASS_PROC_PENTIUM 0x02 |
| 259 | #define PCI_SUBCLASS_PROC_ALPHA 0x10 |
| 260 | #define PCI_SUBCLASS_PROC_POWERPC 0x20 |
| 261 | #define PCI_SUBCLASS_PROC_MIPS 0x30 |
| 262 | #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor |
| 263 | |
| 264 | #define PCI_CLASS_SERIAL 0x0C |
| 265 | #define PCI_CLASS_SERIAL_FIREWIRE 0x00 |
| 266 | #define PCI_IF_1394 0x00 |
| 267 | #define PCI_IF_1394_OPEN_HCI 0x10 |
| 268 | #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01 |
| 269 | #define PCI_CLASS_SERIAL_SSA 0x02 |
| 270 | #define PCI_CLASS_SERIAL_USB 0x03 |
| 271 | #define PCI_IF_UHCI 0x00 |
| 272 | #define PCI_IF_OHCI 0x10 |
| 273 | #define PCI_IF_USB_OTHER 0x80 |
| 274 | #define PCI_IF_USB_DEVICE 0xFE |
| 275 | #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04 |
| 276 | #define PCI_CLASS_SERIAL_SMB 0x05 |
| 277 | |
| 278 | #define PCI_CLASS_WIRELESS 0x0D |
| 279 | #define PCI_SUBCLASS_IRDA 0x00 |
| 280 | #define PCI_SUBCLASS_IR 0x01 |
| 281 | #define PCI_SUBCLASS_RF 0x10 |
| 282 | #define PCI_SUBCLASS_WIRELESS_OTHER 0x80 |
| 283 | |
| 284 | #define PCI_CLASS_INTELLIGENT_IO 0x0E |
| 285 | |
| 286 | #define PCI_CLASS_SATELLITE 0x0F |
| 287 | #define PCI_SUBCLASS_TV 0x01 |
| 288 | #define PCI_SUBCLASS_AUDIO 0x02 |
| 289 | #define PCI_SUBCLASS_VOICE 0x03 |
| 290 | #define PCI_SUBCLASS_DATA 0x04 |
| 291 | |
| 292 | #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller |
| 293 | #define PCI_SUBCLASS_NET_COMPUT 0x00 |
| 294 | #define PCI_SUBCLASS_ENTERTAINMENT 0x10 |
| 295 | #define PCI_SUBCLASS_SECURITY_OTHER 0x80 |
| 296 | |
| 297 | #define PCI_CLASS_DPIO 0x11 |
| 298 | #define PCI_SUBCLASS_DPIO 0x00 |
| 299 | #define PCI_SUBCLASS_DPIO_OTHER 0x80 |
| 300 | |
| 301 | /** |
| 302 | Macro that checks whether the Base Class code of device matched. |
| 303 | |
| 304 | @param _p Specified device. |
| 305 | @param c Base Class code needs matching. |
| 306 | |
| 307 | @retval TRUE Base Class code matches the specified device. |
| 308 | @retval FALSE Base Class code doesn't match the specified device. |
| 309 | |
| 310 | **/ |
| 311 | #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c)) |
| 312 | /** |
| 313 | Macro that checks whether the Base Class code and Sub-Class code of device matched. |
| 314 | |
| 315 | @param _p Specified device. |
| 316 | @param c Base Class code needs matching. |
| 317 | @param s Sub-Class code needs matching. |
| 318 | |
| 319 | @retval TRUE Base Class code and Sub-Class code match the specified device. |
| 320 | @retval FALSE Base Class code and Sub-Class code don't match the specified device. |
| 321 | |
| 322 | **/ |
| 323 | #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s))) |
| 324 | /** |
| 325 | Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched. |
| 326 | |
| 327 | @param _p Specified device. |
| 328 | @param c Base Class code needs matching. |
| 329 | @param s Sub-Class code needs matching. |
| 330 | @param p Interface code needs matching. |
| 331 | |
| 332 | @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device. |
| 333 | @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. |
| 334 | |
| 335 | **/ |
| 336 | #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p))) |
| 337 | |
| 338 | /** |
| 339 | Macro that checks whether device is a display controller. |
| 340 | |
| 341 | @param _p Specified device. |
| 342 | |
| 343 | @retval TRUE Device is a display controller. |
| 344 | @retval FALSE Device is not a display controller. |
| 345 | |
| 346 | **/ |
| 347 | #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY) |
| 348 | /** |
| 349 | Macro that checks whether device is a VGA-compatible controller. |
| 350 | |
| 351 | @param _p Specified device. |
| 352 | |
| 353 | @retval TRUE Device is a VGA-compatible controller. |
| 354 | @retval FALSE Device is not a VGA-compatible controller. |
| 355 | |
| 356 | **/ |
| 357 | #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA) |
| 358 | /** |
| 359 | Macro that checks whether device is an 8514-compatible controller. |
| 360 | |
| 361 | @param _p Specified device. |
| 362 | |
| 363 | @retval TRUE Device is an 8514-compatible controller. |
| 364 | @retval FALSE Device is not an 8514-compatible controller. |
| 365 | |
| 366 | **/ |
| 367 | #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514) |
| 368 | /** |
| 369 | Macro that checks whether device is built before the Class Code field was defined. |
| 370 | |
| 371 | @param _p Specified device. |
| 372 | |
| 373 | @retval TRUE Device is an old device. |
| 374 | @retval FALSE Device is not an old device. |
| 375 | |
| 376 | **/ |
| 377 | #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD) |
| 378 | /** |
| 379 | Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined. |
| 380 | |
| 381 | @param _p Specified device. |
| 382 | |
| 383 | @retval TRUE Device is an old VGA-compatible device. |
| 384 | @retval FALSE Device is not an old VGA-compatible device. |
| 385 | |
| 386 | **/ |
| 387 | #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) |
| 388 | /** |
| 389 | Macro that checks whether device is an IDE controller. |
| 390 | |
| 391 | @param _p Specified device. |
| 392 | |
| 393 | @retval TRUE Device is an IDE controller. |
| 394 | @retval FALSE Device is not an IDE controller. |
| 395 | |
| 396 | **/ |
| 397 | #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE) |
| 398 | /** |
| 399 | Macro that checks whether device is a SCSI bus controller. |
| 400 | |
| 401 | @param _p Specified device. |
| 402 | |
| 403 | @retval TRUE Device is a SCSI bus controller. |
| 404 | @retval FALSE Device is not a SCSI bus controller. |
| 405 | |
| 406 | **/ |
| 407 | #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI) |
| 408 | /** |
| 409 | Macro that checks whether device is a RAID controller. |
| 410 | |
| 411 | @param _p Specified device. |
| 412 | |
| 413 | @retval TRUE Device is a RAID controller. |
| 414 | @retval FALSE Device is not a RAID controller. |
| 415 | |
| 416 | **/ |
| 417 | #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID) |
| 418 | /** |
| 419 | Macro that checks whether device is an ISA bridge. |
| 420 | |
| 421 | @param _p Specified device. |
| 422 | |
| 423 | @retval TRUE Device is an ISA bridge. |
| 424 | @retval FALSE Device is not an ISA bridge. |
| 425 | |
| 426 | **/ |
| 427 | #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA) |
| 428 | /** |
| 429 | Macro that checks whether device is a PCI-to-PCI bridge. |
| 430 | |
| 431 | @param _p Specified device. |
| 432 | |
| 433 | @retval TRUE Device is a PCI-to-PCI bridge. |
| 434 | @retval FALSE Device is not a PCI-to-PCI bridge. |
| 435 | |
| 436 | **/ |
| 437 | #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P) |
| 438 | /** |
| 439 | Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge. |
| 440 | |
| 441 | @param _p Specified device. |
| 442 | |
| 443 | @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge. |
| 444 | @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge. |
| 445 | |
| 446 | **/ |
| 447 | #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE) |
| 448 | /** |
| 449 | Macro that checks whether device is a 16550-compatible serial controller. |
| 450 | |
| 451 | @param _p Specified device. |
| 452 | |
| 453 | @retval TRUE Device is a 16550-compatible serial controller. |
| 454 | @retval FALSE Device is not a 16550-compatible serial controller. |
| 455 | |
| 456 | **/ |
| 457 | #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550) |
| 458 | /** |
| 459 | Macro that checks whether device is a Universal Serial Bus controller. |
| 460 | |
| 461 | @param _p Specified device. |
| 462 | |
| 463 | @retval TRUE Device is a Universal Serial Bus controller. |
| 464 | @retval FALSE Device is not a Universal Serial Bus controller. |
| 465 | |
| 466 | **/ |
| 467 | #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB) |
| 468 | |
| 469 | // |
| 470 | // the definition of Header Type |
| 471 | // |
| 472 | #define HEADER_TYPE_DEVICE 0x00 |
| 473 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01 |
| 474 | #define HEADER_TYPE_CARDBUS_BRIDGE 0x02 |
| 475 | #define HEADER_TYPE_MULTI_FUNCTION 0x80 |
| 476 | // |
| 477 | // Mask of Header type |
| 478 | // |
| 479 | #define HEADER_LAYOUT_CODE 0x7f |
| 480 | /** |
| 481 | Macro that checks whether device is a PCI-PCI bridge. |
| 482 | |
| 483 | @param _p Specified device. |
| 484 | |
| 485 | @retval TRUE Device is a PCI-PCI bridge. |
| 486 | @retval FALSE Device is not a PCI-PCI bridge. |
| 487 | |
| 488 | **/ |
| 489 | #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE)) |
| 490 | /** |
| 491 | Macro that checks whether device is a CardBus bridge. |
| 492 | |
| 493 | @param _p Specified device. |
| 494 | |
| 495 | @retval TRUE Device is a CardBus bridge. |
| 496 | @retval FALSE Device is not a CardBus bridge. |
| 497 | |
| 498 | **/ |
| 499 | #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) |
| 500 | /** |
| 501 | Macro that checks whether device is a multiple functions device. |
| 502 | |
| 503 | @param _p Specified device. |
| 504 | |
| 505 | @retval TRUE Device is a multiple functions device. |
| 506 | @retval FALSE Device is not a multiple functions device. |
| 507 | |
| 508 | **/ |
| 509 | #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION) |
| 510 | |
| 511 | /// |
| 512 | /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification, |
| 513 | /// |
| 514 | #define PCI_BRIDGE_ROMBAR 0x38 |
| 515 | |
| 516 | #define PCI_MAX_BAR 0x0006 |
| 517 | #define PCI_MAX_CONFIG_OFFSET 0x0100 |
| 518 | |
| 519 | #define PCI_VENDOR_ID_OFFSET 0x00 |
| 520 | #define PCI_DEVICE_ID_OFFSET 0x02 |
| 521 | #define PCI_COMMAND_OFFSET 0x04 |
| 522 | #define PCI_PRIMARY_STATUS_OFFSET 0x06 |
| 523 | #define PCI_REVISION_ID_OFFSET 0x08 |
| 524 | #define PCI_CLASSCODE_OFFSET 0x09 |
| 525 | #define PCI_CACHELINE_SIZE_OFFSET 0x0C |
| 526 | #define PCI_LATENCY_TIMER_OFFSET 0x0D |
| 527 | #define PCI_HEADER_TYPE_OFFSET 0x0E |
| 528 | #define PCI_BIST_OFFSET 0x0F |
| 529 | #define PCI_BASE_ADDRESSREG_OFFSET 0x10 |
| 530 | #define PCI_CARDBUS_CIS_OFFSET 0x28 |
| 531 | #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id |
| 532 | #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C |
| 533 | #define PCI_SID_OFFSET 0x2E ///< SubSystem ID |
| 534 | #define PCI_SUBSYSTEM_ID_OFFSET 0x2E |
| 535 | #define PCI_EXPANSION_ROM_BASE 0x30 |
| 536 | #define PCI_CAPBILITY_POINTER_OFFSET 0x34 |
| 537 | #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register |
| 538 | #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register |
| 539 | #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register |
| 540 | #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register |
| 541 | |
| 542 | // |
| 543 | // defined in PCI-to-PCI Bridge Architecture Specification |
| 544 | // |
| 545 | #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 |
| 546 | #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 |
| 547 | #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a |
| 548 | #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b |
| 549 | #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E |
| 550 | #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E |
| 551 | |
| 552 | /// |
| 553 | /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system |
| 554 | /// |
| 555 | #define PCI_INT_LINE_UNKNOWN 0xFF |
| 556 | |
| 557 | /// |
| 558 | /// PCI Access Data Format |
| 559 | /// |
| 560 | typedef union { |
| 561 | struct { |
| 562 | UINT32 Reg : 8; |
| 563 | UINT32 Func : 3; |
| 564 | UINT32 Dev : 5; |
| 565 | UINT32 Bus : 8; |
| 566 | UINT32 Reserved : 7; |
| 567 | UINT32 Enable : 1; |
| 568 | } Bits; |
| 569 | UINT32 Uint32; |
| 570 | } PCI_CONFIG_ACCESS_CF8; |
| 571 | |
| 572 | #pragma pack() |
| 573 | |
| 574 | #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001 |
| 575 | #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002 |
| 576 | #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004 |
| 577 | #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008 |
| 578 | #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010 |
| 579 | #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020 |
| 580 | #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040 |
| 581 | #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080 |
| 582 | #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100 |
| 583 | #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200 |
| 584 | |
| 585 | // |
| 586 | // defined in PCI-to-PCI Bridge Architecture Specification |
| 587 | // |
| 588 | #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001 |
| 589 | #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002 |
| 590 | #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004 |
| 591 | #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008 |
| 592 | #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010 |
| 593 | #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020 |
| 594 | #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040 |
| 595 | #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080 |
| 596 | #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100 |
| 597 | #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200 |
| 598 | #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400 |
| 599 | #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800 |
| 600 | |
| 601 | // |
| 602 | // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard |
| 603 | // |
| 604 | #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080 |
| 605 | #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100 |
| 606 | #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200 |
| 607 | #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400 |
| 608 | |
| 609 | // |
| 610 | // Following are the PCI status control bit |
| 611 | // |
| 612 | #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010 |
| 613 | #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020 |
| 614 | #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080 |
| 615 | #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100 |
| 616 | |
| 617 | /// |
| 618 | /// defined in PC Card Standard |
| 619 | /// |
| 620 | #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14 |
| 621 | |
| 622 | #pragma pack(1) |
| 623 | // |
| 624 | // PCI Capability List IDs and records |
| 625 | // |
| 626 | #define EFI_PCI_CAPABILITY_ID_PMI 0x01 |
| 627 | #define EFI_PCI_CAPABILITY_ID_AGP 0x02 |
| 628 | #define EFI_PCI_CAPABILITY_ID_VPD 0x03 |
| 629 | #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04 |
| 630 | #define EFI_PCI_CAPABILITY_ID_MSI 0x05 |
| 631 | #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06 |
| 632 | #define EFI_PCI_CAPABILITY_ID_SHPC 0x0C |
| 633 | |
| 634 | /// |
| 635 | /// Capabilities List Header |
| 636 | /// Section 6.7, PCI Local Bus Specification, 2.2 |
| 637 | /// |
| 638 | typedef struct { |
| 639 | UINT8 CapabilityID; |
| 640 | UINT8 NextItemPtr; |
| 641 | } EFI_PCI_CAPABILITY_HDR; |
| 642 | |
| 643 | /// |
| 644 | /// PMC - Power Management Capabilities |
| 645 | /// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2 |
| 646 | /// |
| 647 | typedef union { |
| 648 | struct { |
| 649 | UINT16 Version : 3; |
| 650 | UINT16 PmeClock : 1; |
| 651 | UINT16 Reserved : 1; |
| 652 | UINT16 DeviceSpecificInitialization : 1; |
| 653 | UINT16 AuxCurrent : 3; |
| 654 | UINT16 D1Support : 1; |
| 655 | UINT16 D2Support : 1; |
| 656 | UINT16 PmeSupport : 5; |
| 657 | } Bits; |
| 658 | UINT16 Data; |
| 659 | } EFI_PCI_PMC; |
| 660 | |
| 661 | #define EFI_PCI_PMC_D3_COLD_MASK (BIT15) |
| 662 | |
| 663 | /// |
| 664 | /// PMCSR - Power Management Control/Status |
| 665 | /// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2 |
| 666 | /// |
| 667 | typedef union { |
| 668 | struct { |
| 669 | UINT16 PowerState : 2; |
| 670 | UINT16 ReservedForPciExpress : 1; |
| 671 | UINT16 NoSoftReset : 1; |
| 672 | UINT16 Reserved : 4; |
| 673 | UINT16 PmeEnable : 1; |
| 674 | UINT16 DataSelect : 4; |
| 675 | UINT16 DataScale : 2; |
| 676 | UINT16 PmeStatus : 1; |
| 677 | } Bits; |
| 678 | UINT16 Data; |
| 679 | } EFI_PCI_PMCSR; |
| 680 | |
| 681 | #define PCI_POWER_STATE_D0 0 |
| 682 | #define PCI_POWER_STATE_D1 1 |
| 683 | #define PCI_POWER_STATE_D2 2 |
| 684 | #define PCI_POWER_STATE_D3_HOT 3 |
| 685 | |
| 686 | /// |
| 687 | /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions |
| 688 | /// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2 |
| 689 | /// |
| 690 | typedef union { |
| 691 | struct { |
| 692 | UINT8 Reserved : 6; |
| 693 | UINT8 B2B3 : 1; |
| 694 | UINT8 BusPowerClockControl : 1; |
| 695 | } Bits; |
| 696 | UINT8 Uint8; |
| 697 | } EFI_PCI_PMCSR_BSE; |
| 698 | |
| 699 | /// |
| 700 | /// Power Management Register Block Definition |
| 701 | /// Section 3.2, PCI Power Management Interface Specification, Revision 1.2 |
| 702 | /// |
| 703 | typedef struct { |
| 704 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 705 | EFI_PCI_PMC PMC; |
| 706 | EFI_PCI_PMCSR PMCSR; |
| 707 | EFI_PCI_PMCSR_BSE BridgeExtention; |
| 708 | UINT8 Data; |
| 709 | } EFI_PCI_CAPABILITY_PMI; |
| 710 | |
| 711 | /// |
| 712 | /// A.G.P Capability |
| 713 | /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0 |
| 714 | /// |
| 715 | typedef struct { |
| 716 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 717 | UINT8 Rev; |
| 718 | UINT8 Reserved; |
| 719 | UINT32 Status; |
| 720 | UINT32 Command; |
| 721 | } EFI_PCI_CAPABILITY_AGP; |
| 722 | |
| 723 | /// |
| 724 | /// VPD Capability Structure |
| 725 | /// Appendix I, PCI Local Bus Specification, 2.2 |
| 726 | /// |
| 727 | typedef struct { |
| 728 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 729 | UINT16 AddrReg; |
| 730 | UINT32 DataReg; |
| 731 | } EFI_PCI_CAPABILITY_VPD; |
| 732 | |
| 733 | /// |
| 734 | /// Slot Numbering Capabilities Register |
| 735 | /// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2 |
| 736 | /// |
| 737 | typedef struct { |
| 738 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 739 | UINT8 ExpnsSlotReg; |
| 740 | UINT8 ChassisNo; |
| 741 | } EFI_PCI_CAPABILITY_SLOTID; |
| 742 | |
| 743 | /// |
| 744 | /// Message Capability Structure for 32-bit Message Address |
| 745 | /// Section 6.8.1, PCI Local Bus Specification, 2.2 |
| 746 | /// |
| 747 | typedef struct { |
| 748 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 749 | UINT16 MsgCtrlReg; |
| 750 | UINT32 MsgAddrReg; |
| 751 | UINT16 MsgDataReg; |
| 752 | } EFI_PCI_CAPABILITY_MSI32; |
| 753 | |
| 754 | /// |
| 755 | /// Message Capability Structure for 64-bit Message Address |
| 756 | /// Section 6.8.1, PCI Local Bus Specification, 2.2 |
| 757 | /// |
| 758 | typedef struct { |
| 759 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 760 | UINT16 MsgCtrlReg; |
| 761 | UINT32 MsgAddrRegLsdw; |
| 762 | UINT32 MsgAddrRegMsdw; |
| 763 | UINT16 MsgDataReg; |
| 764 | } EFI_PCI_CAPABILITY_MSI64; |
| 765 | |
| 766 | /// |
| 767 | /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, |
| 768 | /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0 |
| 769 | /// |
| 770 | typedef struct { |
| 771 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 772 | /// |
| 773 | /// not finished - fields need to go here |
| 774 | /// |
| 775 | } EFI_PCI_CAPABILITY_HOTPLUG; |
| 776 | |
| 777 | #define PCI_BAR_IDX0 0x00 |
| 778 | #define PCI_BAR_IDX1 0x01 |
| 779 | #define PCI_BAR_IDX2 0x02 |
| 780 | #define PCI_BAR_IDX3 0x03 |
| 781 | #define PCI_BAR_IDX4 0x04 |
| 782 | #define PCI_BAR_IDX5 0x05 |
| 783 | |
| 784 | /// |
| 785 | /// EFI PCI Option ROM definitions |
| 786 | /// |
| 787 | #define EFI_ROOT_BRIDGE_LIST 'eprb' |
| 788 | #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec. |
| 789 | |
| 790 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55 |
| 791 | #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R') |
| 792 | #define PCI_CODE_TYPE_PCAT_IMAGE 0x00 |
| 793 | #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec. |
| 794 | |
| 795 | /// |
| 796 | /// Standard PCI Expansion ROM Header |
| 797 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1 |
| 798 | /// |
| 799 | typedef struct { |
| 800 | UINT16 Signature; ///< 0xaa55 |
| 801 | UINT8 Reserved[0x16]; |
| 802 | UINT16 PcirOffset; |
| 803 | } PCI_EXPANSION_ROM_HEADER; |
| 804 | |
| 805 | /// |
| 806 | /// Legacy ROM Header Extensions |
| 807 | /// Section 6.3.3.1, PCI Local Bus Specification, 2.2 |
| 808 | /// |
| 809 | typedef struct { |
| 810 | UINT16 Signature; ///< 0xaa55 |
| 811 | UINT8 Size512; |
| 812 | UINT8 InitEntryPoint[3]; |
| 813 | UINT8 Reserved[0x12]; |
| 814 | UINT16 PcirOffset; |
| 815 | } EFI_LEGACY_EXPANSION_ROM_HEADER; |
| 816 | |
| 817 | /// |
| 818 | /// PCI Data Structure Format |
| 819 | /// Section 6.3.1.2, PCI Local Bus Specification, 2.2 |
| 820 | /// |
| 821 | typedef struct { |
| 822 | UINT32 Signature; ///< "PCIR" |
| 823 | UINT16 VendorId; |
| 824 | UINT16 DeviceId; |
| 825 | UINT16 Reserved0; |
| 826 | UINT16 Length; |
| 827 | UINT8 Revision; |
| 828 | UINT8 ClassCode[3]; |
| 829 | UINT16 ImageLength; |
| 830 | UINT16 CodeRevision; |
| 831 | UINT8 CodeType; |
| 832 | UINT8 Indicator; |
| 833 | UINT16 Reserved1; |
| 834 | } PCI_DATA_STRUCTURE; |
| 835 | |
| 836 | /// |
| 837 | /// EFI PCI Expansion ROM Header |
| 838 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1 |
| 839 | /// |
| 840 | typedef struct { |
| 841 | UINT16 Signature; ///< 0xaa55 |
| 842 | UINT16 InitializationSize; |
| 843 | UINT32 EfiSignature; ///< 0x0EF1 |
| 844 | UINT16 EfiSubsystem; |
| 845 | UINT16 EfiMachineType; |
| 846 | UINT16 CompressionType; |
| 847 | UINT8 Reserved[8]; |
| 848 | UINT16 EfiImageHeaderOffset; |
| 849 | UINT16 PcirOffset; |
| 850 | } EFI_PCI_EXPANSION_ROM_HEADER; |
| 851 | |
| 852 | typedef union { |
| 853 | UINT8 *Raw; |
| 854 | PCI_EXPANSION_ROM_HEADER *Generic; |
| 855 | EFI_PCI_EXPANSION_ROM_HEADER *Efi; |
| 856 | EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt; |
| 857 | } EFI_PCI_ROM_HEADER; |
| 858 | |
| 859 | #pragma pack() |
| 860 | |
| 861 | #endif |