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review.coreboot.org / coreboot / 20a98c9201a0a3699e64c2c2dc4c6259ae948ade / . / src / mainboard / via / epia-m700 / DrivingClkPhaseData.c
blob: 06f1a8eaaa1071909c3eba9f9a3eca337aa658e6 [file] [log] [blame]
Uwe Hermann20a98c92009-06-05 23:02:43 +0000[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include "northbridge/via/vx800/DrivingClkPhaseData.h"
22
23// DQS Driving
24//Reg0xE0, 0xE1
25// According to #Bank to set DRAM DQS Driving
26// #Bank 1 2 3 4 5 6 7 8
27static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE};
28static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE};
29
30// DQ Driving
31//Reg0xE2, 0xE3
32// For DDR2: According to bank to set DRAM DQ Driving
33static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC };
34static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA };
35
36
37// CS Driving
38//Reg0xE4, 0xE5
39// According to #Bank to set DRAM CS Driving
40// DDR1 #Bank 1 2 3 4 5 6 7 8
41static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 };
42static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44};
43static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44};
44static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44};
45// MAA Driving
46//Reg0xE8, Reg0xE9
47static const u8 DDR2_MAA_Driving_Table[MA_Table][5] =
48 {
49 //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8
50 { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06
51 { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18
52 {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~
53 };
54
55static const u8 DDR2_MAB_Driving_Table[MA_Table][2] =
56 {
57 // Chip number, Value ;(SRAS, SCAS, SWE)RxE9
58 { 6, 0x86 }, // total MAB chips = 00 ~ 06
59 { 18, 0x86 }, // total MAB chips = 06 ~ 18
60 {255, 0xDB } // total MAB chips = 18 ~
61 };
62
63// DCLK Driving
64//Reg0xE6, 0xE7
65// For DDR2: According to #Freq to set DRAM DCLK Driving
66// freq 400M, 533M, 667M, 800M
67
68static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
69static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
70
71/*
72Duty cycle
73Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB
74D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF
75According to DRAM frequency to control Duty Cycle
76*/
77static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
78 {
79 // (And NOT) DDR800 DDR667 DDR533 DDR400
80 //Reg Mask Value Value Value Value
81 {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank
82 {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 },
83 {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}
84 };
85
86static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
87 {
88 // (And NOT) DDR800 DDR667 DDR533 DDR400
89 //Reg Mask Value Value Value Value
90 {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank
91 {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 },
92 {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 }
93 };
94
95
96/*
97DRAM Clock Phase Control for FeedBack Mode
98Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94
99Processing:
100 1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode
101 2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b
102 3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO
103 ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b
104 */
105static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
106 {
107 // (And NOT) DDR800 DDR667 DDR533 DDR400
108 //Reg Mask Value Value Value Value
109 {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank
110 {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
111 {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
112 };
113
114static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
115 {
116 // (And NOT) DDR800 DDR667 DDR533 DDR400
117 //Reg Mask Value Value Value Value
118 {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank
119 {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 },
120 {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 }
121 };
122
123//vt6413c
124/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] =
125 {
126 // (And NOT) DDR800 DDR667 DDR533 DDR400
127 //Reg Mask Value Value Value Value
128 {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank
129 {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 },
130 {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 }
131 };*/
132
133//vt6413d
134static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] =
135 {
136 // (And NOT) DDR800 DDR667 DDR533 DDR400
137 //Reg Mask Value Value Value Value
138 {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
139 {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
140 {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
141 };
142
143/*
144DRAM Write Data phase control
145Modify NB Reg: Rx74/Rx75/Rx76
146*/
147//vt6413c
148/*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
149 {
150 // (And NOT) DDR800 DDR667 DDR533 DDR400
151 //Reg Mask Value Value Value Value
152 {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank
153 {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 },
154 {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 }
155 };*/
156
157//vt6413D
158static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
159 {
160 // (And NOT) DDR800 DDR667 DDR533 DDR400
161 //Reg Mask Value Value Value Value
162 {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank
163 {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 },
164 {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 },
165 {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 }
166 };
167
168/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
169 {
170 // (And NOT) DDR800 DDR667 DDR533 DDR400
171 //Reg Mask Value Value Value Value
172 {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank
173 {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 },
174 {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }
175 };
176*/
177/*
178DQ/DQS Output Delay Control
179Modify NB D0F3: RxF0/RxF1/RxF2/RxF3
180*/
181static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
182 {
183 // RxF0 RxF1 RxF2 RxF3
184 { 0x00, 0x00, 0x00, 0x00 },// DDR400
185 { 0x00, 0x00, 0x00, 0x00 },// DDR533
186 { 0x00, 0x00, 0x00, 0x00 },// DDR667
187 { 0x00, 0x00, 0x00, 0x00 }// DDR800
188 };
189static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
190 {
191 // RxF4 RxF5 RxF6 RxF7
192 { 0x00, 0x00, 0x00, 0x00 },// DDR400
193 { 0x00, 0x00, 0x00, 0x00 },// DDR533
194 { 0x00, 0x00, 0x00, 0x00 },// DDR667
195 { 0x00, 0x00, 0x00, 0x00 }// DDR800
196 };
197
198/*
199DQ/DQS input Capture Control
200modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B
201*/
202//vt6413C
203/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
204 {
205 // (And NOT) DDR800 DDR667 DDR533 DDR400
206 //Reg Mask Value Value Value Value
207 {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank
208 {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
209 {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 }
210 };*/
211
212//Vt6413D
213static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
214 {
215 // (And NOT) DDR800 DDR667 DDR533 DDR400
216 //Reg Mask Value Value Value Value
217 {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank
218 {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
219 {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 }
220 };
221
222static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
223 {
224 // (And NOT) DDR800 DDR667 DDR533 DDR400
225 //Reg Mask Value Value Value Value
226 {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank
227 {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 },
228 {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 }
229 };
230
231static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] =
232{
233// Rx70 Rx71
234 { 0x00, 0x05 }, // DDR800
235 { 0x00, 0x06 }, // DDR667
236 { 0x00, 0x04 }, // DDR533
237 { 0x00, 0x05 } // DDR400
238};
239static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] =
240{
241// Rx70 Rx71
242 {0x00 , 0x04}, // DDR800
243 {0x00 , 0x04}, // DDR667
244 {0x00 , 0x03}, // DDR533
245 {0x00 , 0x04} // DDR400
246};