Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 1 | # Warning: This file is included whether or not the if is here. |
| 2 | # The if controls how the evaluation occurs. |
| 3 | # (See also src/Kconfig) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 4 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 5 | source "src/cpu/*/Kconfig" |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 6 | |
Furquan Shaikh | fd33781 | 2014-04-22 15:16:54 -0700 | [diff] [blame] | 7 | if ARCH_X86 |
| 8 | |
Stefan Reinauer | 704b596 | 2010-08-30 17:53:13 +0000 | [diff] [blame] | 9 | config CACHE_AS_RAM |
Patrick Georgi | 39ec29c | 2009-08-27 12:10:50 +0000 | [diff] [blame] | 10 | bool |
Stefan Reinauer | 314e551 | 2010-04-09 20:36:29 +0000 | [diff] [blame] | 11 | default !ROMCC |
Patrick Georgi | 39ec29c | 2009-08-27 12:10:50 +0000 | [diff] [blame] | 12 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 13 | config DCACHE_RAM_BASE |
| 14 | hex |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 15 | |
| 16 | config DCACHE_RAM_SIZE |
| 17 | hex |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 18 | |
Timothy Pearson | b5e4655 | 2015-06-02 13:47:36 -0500 | [diff] [blame] | 19 | config DCACHE_BSP_STACK_SIZE |
| 20 | hex |
| 21 | |
Timothy Pearson | fb39f82 | 2015-06-02 20:25:03 -0500 | [diff] [blame] | 22 | config DCACHE_BSP_STACK_SLUSH |
| 23 | hex |
| 24 | |
Timothy Pearson | b5e4655 | 2015-06-02 13:47:36 -0500 | [diff] [blame] | 25 | config DCACHE_AP_STACK_SIZE |
| 26 | hex |
| 27 | |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 28 | config SMP |
| 29 | bool |
Myles Watson | 45bb25f | 2009-09-22 18:49:08 +0000 | [diff] [blame] | 30 | default y if MAX_CPUS != 1 |
Patrick Georgi | 892b091 | 2009-09-24 09:03:06 +0000 | [diff] [blame] | 31 | default n |
Uwe Hermann | a29ad5c | 2009-10-18 18:35:50 +0000 | [diff] [blame] | 32 | help |
| 33 | This option is used to enable certain functions to make coreboot |
| 34 | work correctly on symmetric multi processor (SMP) systems. |
Ronald G. Minnich | 149d675 | 2009-10-01 23:22:50 +0000 | [diff] [blame] | 35 | |
Kyösti Mälkki | 7dfe32c | 2012-02-14 10:39:17 +0200 | [diff] [blame] | 36 | config AP_SIPI_VECTOR |
| 37 | hex |
| 38 | default 0xfffff000 |
| 39 | help |
| 40 | This must equal address of ap_sipi_vector from bootblock build. |
Patrick Georgi | 819c7d4 | 2012-03-31 13:08:12 +0200 | [diff] [blame] | 41 | |
Ronald G. Minnich | 149d675 | 2009-10-01 23:22:50 +0000 | [diff] [blame] | 42 | config MMX |
| 43 | bool |
Stefan Reinauer | a7acc51 | 2010-02-25 13:40:49 +0000 | [diff] [blame] | 44 | help |
| 45 | Select MMX in your socket or model Kconfig if your CPU has MMX |
| 46 | streaming SIMD instructions. ROMCC can build more efficient |
| 47 | code if it can spill to MMX registers. |
Ronald G. Minnich | 149d675 | 2009-10-01 23:22:50 +0000 | [diff] [blame] | 48 | |
| 49 | config SSE |
| 50 | bool |
Stefan Reinauer | a7acc51 | 2010-02-25 13:40:49 +0000 | [diff] [blame] | 51 | help |
| 52 | Select SSE in your socket or model Kconfig if your CPU has SSE |
| 53 | streaming SIMD instructions. ROMCC can build more efficient |
| 54 | code if it can spill to SSE (aka XMM) registers. |
| 55 | |
| 56 | config SSE2 |
| 57 | bool |
Myles Watson | 3426195 | 2010-03-19 02:33:40 +0000 | [diff] [blame] | 58 | default n |
Stefan Reinauer | a7acc51 | 2010-02-25 13:40:49 +0000 | [diff] [blame] | 59 | help |
| 60 | Select SSE2 in your socket or model Kconfig if your CPU has SSE2 |
| 61 | streaming SIMD instructions. Some parts of coreboot can be built |
| 62 | with more efficient code if SSE2 instructions are available. |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 63 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 64 | endif # ARCH_X86 |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 65 | |
Alexandru Gagniuc | 66e0c4c | 2013-12-04 22:21:15 -0600 | [diff] [blame] | 66 | config SUPPORT_CPU_UCODE_IN_CBFS |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 67 | bool |
| 68 | default n |
| 69 | |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 70 | config USES_MICROCODE_HEADER_FILES |
| 71 | def_bool n |
| 72 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 73 | help |
| 74 | This is selected by a board or chipset to set the default for the |
| 75 | microcode source choice to a list of external microcode headers |
| 76 | |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 77 | choice |
Stefan Reinauer | 9c29cfa | 2013-02-27 20:24:11 +0100 | [diff] [blame] | 78 | prompt "Include CPU microcode in CBFS" if ARCH_X86 |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 79 | default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES |
Paul Menzel | bdaeea5 | 2015-03-07 09:15:02 +0100 | [diff] [blame] | 80 | default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS |
Alexandru Gagniuc | 66e0c4c | 2013-12-04 22:21:15 -0600 | [diff] [blame] | 81 | default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 82 | |
| 83 | config CPU_MICROCODE_CBFS_GENERATE |
| 84 | bool "Generate from tree" |
| 85 | help |
| 86 | Select this option if you want microcode updates to be assembled when |
| 87 | building coreboot and included in the final image as a separate CBFS |
| 88 | file. Microcode will not be hard-coded into ramstage. |
| 89 | |
Stefan Tauner | 0ce2b43 | 2013-04-01 13:45:44 +0200 | [diff] [blame] | 90 | The microcode file may be removed from the ROM image at a later |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 91 | time with cbfstool, if desired. |
| 92 | |
| 93 | If unsure, select this option. |
| 94 | |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 95 | config CPU_MICROCODE_CBFS_EXTERNAL_HEADER |
| 96 | bool "Include external microcode header files" |
| 97 | help |
| 98 | Select this option if you want to include external c header files |
| 99 | containing the CPU microcode. This will be included as a separate |
| 100 | file in CBFS. |
| 101 | |
| 102 | A word of caution: only select this option if you are sure the |
| 103 | microcode that you have is newer than the microcode shipping with |
| 104 | coreboot. |
| 105 | |
| 106 | The microcode file may be removed from the ROM image at a later |
| 107 | time with cbfstool, if desired. |
| 108 | |
| 109 | If unsure, select "Generate from tree" |
| 110 | |
Alexandru Gagniuc | 00b579a | 2012-07-20 00:11:21 -0500 | [diff] [blame] | 111 | config CPU_MICROCODE_CBFS_NONE |
| 112 | bool "Do not include microcode updates" |
| 113 | help |
| 114 | Select this option if you do not want CPU microcode included in CBFS. |
| 115 | Note that for some CPUs, the microcode is hard-coded into the source |
| 116 | tree and is not loaded from CBFS. In this case, microcode will still |
| 117 | be updated. There is a push to move all microcode to CBFS, but this |
| 118 | change is not implemented for all CPUs. |
| 119 | |
| 120 | This option currently applies to: |
| 121 | - Intel SandyBridge/IvyBridge |
| 122 | - VIA Nano |
| 123 | |
| 124 | Microcode may be added to the ROM image at a later time with cbfstool, |
| 125 | if desired. |
| 126 | |
| 127 | If unsure, select "Generate from tree" |
| 128 | |
| 129 | The GOOD: |
| 130 | Microcode updates intend to solve issues that have been discovered |
| 131 | after CPU production. The expected effect is that systems work as |
| 132 | intended with the updated microcode, but we have also seen cases where |
| 133 | issues were solved by not applying microcode updates. |
| 134 | |
| 135 | The BAD: |
| 136 | Note that some operating system include these same microcode patches, |
| 137 | so you may need to also disable microcode updates in your operating |
| 138 | system for this option to have an effect. |
| 139 | |
| 140 | The UGLY: |
| 141 | A word of CAUTION: some CPUs depend on microcode updates to function |
| 142 | correctly. Not updating the microcode may leave the CPU operating at |
| 143 | less than optimal performance, or may cause outright hangups. |
| 144 | There are CPUs where coreboot cannot properly initialize the CPU |
| 145 | without microcode updates |
| 146 | For example, if running with the factory microcode, some Intel |
| 147 | SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs |
| 148 | will hang when changing the frequency. |
| 149 | |
| 150 | Make sure you have a way of flashing the ROM externally before |
| 151 | selecting this option. |
| 152 | |
| 153 | endchoice |
Jens Rottmann | 686dc0d | 2013-02-18 17:26:01 +0100 | [diff] [blame] | 154 | |
Timothy Pearson | 24e6d04 | 2015-10-08 16:58:58 -0500 | [diff] [blame] | 155 | config CPU_MICROCODE_MULTIPLE_FILES |
| 156 | bool |
| 157 | default n |
| 158 | depends on CPU_MICROCODE_CBFS_GENERATE |
| 159 | help |
| 160 | Select this option to install separate microcode container files into |
| 161 | CBFS instead of using the traditional monolithic microcode file format. |
Martin Roth | 4c50269 | 2015-11-05 08:03:45 -0700 | [diff] [blame] | 162 | |
| 163 | config CPU_MICROCODE_HEADER_FILES |
| 164 | string "List of space separated microcode header files with the path" |
| 165 | depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER |
| 166 | help |
| 167 | A list of one or more microcode header files with path from the |
| 168 | coreboot directory. These should be separated by spaces. |