Nico Huber | 1f6bd94 | 2012-08-30 15:36:57 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the libpayload project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | //#define DEBUG_STATUS |
| 31 | |
| 32 | #include <stdlib.h> |
| 33 | #include <stdint.h> |
| 34 | #include <string.h> |
| 35 | #include <libpayload.h> |
| 36 | #include <pci.h> |
| 37 | #include <storage/ata.h> |
| 38 | #include <storage/ahci.h> |
| 39 | |
| 40 | #include "ahci_private.h" |
| 41 | |
| 42 | |
| 43 | #ifdef DEBUG_STATUS |
| 44 | static inline u32 _ahci_clear_status(volatile u32 *const reg, |
| 45 | const char *const r, |
| 46 | const char *const f) |
| 47 | { |
| 48 | const u32 bits = *reg; |
| 49 | if (bits) |
| 50 | *reg = bits; |
| 51 | printf("ahci: %s: %s == 0x%08x\n", f, r, bits); |
| 52 | |
| 53 | return bits; |
| 54 | } |
| 55 | #define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r, #r, __func__) |
| 56 | #else |
| 57 | static inline u32 _ahci_clear_status(volatile u32 *const reg) |
| 58 | { |
| 59 | const u32 bits = *reg; |
| 60 | if (bits) |
| 61 | *reg = bits; |
| 62 | return bits; |
| 63 | } |
| 64 | #define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r) |
| 65 | #endif |
| 66 | |
| 67 | |
| 68 | static inline int ahci_port_is_active(const hba_port_t *const port) |
| 69 | { |
| 70 | return (port->sata_status & (HBA_PxSSTS_IPM_MASK | HBA_PxSSTS_DET_MASK)) |
| 71 | == (HBA_PxSSTS_IPM_ACTIVE | HBA_PxSSTS_DET_ESTABLISHED); |
| 72 | } |
| 73 | |
| 74 | static int ahci_cmdengine_start(hba_port_t *const port) |
| 75 | { |
| 76 | /* Wait for the controller to clear CR. |
| 77 | This shouldn't take too long, but we should time out nevertheless. */ |
| 78 | int timeout = 1000; /* Time out after 1000 * 1us == 1ms. */ |
| 79 | while ((port->cmd_stat & HBA_PxCMD_CR) && timeout--) |
| 80 | udelay(1); |
| 81 | if (timeout < 0) { |
| 82 | printf("ahci: Timeout during start of command engine.\n"); |
| 83 | return 1; |
| 84 | } |
| 85 | |
| 86 | port->cmd_stat |= HBA_PxCMD_FRE; |
| 87 | port->cmd_stat |= HBA_PxCMD_ST; |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | static int ahci_cmdengine_stop(hba_port_t *const port) |
| 92 | { |
| 93 | port->cmd_stat &= ~HBA_PxCMD_ST; |
| 94 | |
| 95 | /* Wait for the controller to clear FR and CR. |
| 96 | This shouldn't take too long, but we should time out nevertheless. */ |
| 97 | int timeout = 1000; /* Time out after 1000 * 1us == 1ms. */ |
| 98 | while ((port->cmd_stat & (HBA_PxCMD_FR | HBA_PxCMD_CR)) && timeout--) |
| 99 | udelay(1); |
| 100 | if (timeout < 0) { |
| 101 | printf("ahci: Timeout during stopping of command engine.\n"); |
| 102 | return 1; |
| 103 | } |
| 104 | |
| 105 | port->cmd_stat &= ~HBA_PxCMD_FRE; |
| 106 | return 0; |
| 107 | } |
| 108 | |
| 109 | /** Do minimal error recovery. */ |
| 110 | static int ahci_error_recovery(ahci_dev_t *const dev, const u32 intr_status) |
| 111 | { |
| 112 | /* Command engine has to be restarted. |
| 113 | We don't call ahci_cmdengine_stop() here as it also checks |
| 114 | HBA_PxCMD_FR which won't clear on fatal errors. */ |
| 115 | dev->port->cmd_stat &= ~HBA_PxCMD_ST; |
| 116 | |
| 117 | /* Always clear sata_error. */ |
| 118 | ahci_clear_status(dev->port, sata_error); |
| 119 | |
| 120 | /* Perform COMRESET if appropriate. */ |
| 121 | const u32 tfd = dev->port->taskfile_data; |
| 122 | if ((tfd & (HBA_PxTFD_BSY | HBA_PxTFD_DRQ)) | |
| 123 | (intr_status & HBA_PxIS_PCS)) { |
| 124 | const u32 sctl = dev->port->sata_control & ~HBA_PxSCTL_DET_MASK; |
| 125 | dev->port->sata_control = sctl | HBA_PxSCTL_DET_COMRESET; |
| 126 | mdelay(1); |
| 127 | dev->port->sata_control = sctl; |
| 128 | } |
| 129 | |
| 130 | if (ahci_port_is_active(dev->port)) |
| 131 | /* Start command engine. */ |
| 132 | return ahci_cmdengine_start(dev->port); |
| 133 | else |
| 134 | return -1; |
| 135 | } |
| 136 | |
| 137 | /** Give a buffer with even address. */ |
| 138 | static u8 *ahci_prdbuf_init(ahci_dev_t *const dev, |
| 139 | u8 *const user_buf, const size_t len, |
| 140 | const int out) |
| 141 | { |
| 142 | if ((u32)user_buf & 1) { |
| 143 | printf("ahci: Odd buffer pointer (%p).\n", user_buf); |
| 144 | if (dev->buf) /* orphaned buffer */ |
| 145 | free((void *)dev->buf - *(dev->buf - 1)); |
| 146 | dev->buf = malloc(len + 2); |
| 147 | if (!dev->buf) |
| 148 | return NULL; |
| 149 | dev->user_buf = user_buf; |
| 150 | dev->write_back = !out; |
| 151 | dev->buflen = len; |
| 152 | if ((u32)dev->buf & 1) { |
| 153 | dev->buf[0] = 1; |
| 154 | dev->buf += 1; |
| 155 | } else { |
| 156 | dev->buf[0] = 1; |
| 157 | dev->buf[1] = 2; |
| 158 | dev->buf += 2; |
| 159 | } |
| 160 | if (out) |
| 161 | memcpy(dev->buf, user_buf, len); |
| 162 | return dev->buf; |
| 163 | } else { |
| 164 | return user_buf; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | static void ahci_prdbuf_finalize(ahci_dev_t *const dev) |
| 169 | { |
| 170 | if (dev->buf) { |
| 171 | if (dev->write_back) |
| 172 | memcpy(dev->user_buf, dev->buf, dev->buflen); |
| 173 | free((void *)dev->buf - *(dev->buf - 1)); |
| 174 | } |
| 175 | dev->buf = NULL; |
| 176 | dev->user_buf = NULL; |
| 177 | dev->write_back = 0; |
| 178 | dev->buflen = 0; |
| 179 | } |
| 180 | |
| 181 | static ssize_t ahci_cmdslot_exec(ahci_dev_t *const dev) |
| 182 | { |
| 183 | const int slotnum = 0; /* We always use the first slot. */ |
| 184 | |
| 185 | if (!(dev->port->cmd_stat & HBA_PxCMD_CR)) |
| 186 | return -1; |
| 187 | |
| 188 | /* Trigger command execution. */ |
| 189 | dev->port->cmd_issue |= (1 << slotnum); |
| 190 | |
| 191 | /* Wait for the controller to finish command execution. */ |
| 192 | int timeout = 50000; /* Time out after 50000 * 100us == 5s. */ |
| 193 | while ((dev->port->cmd_issue & (1 << slotnum)) && |
| 194 | !(dev->port->intr_status & HBA_PxIS_TFES) && |
| 195 | timeout--) |
| 196 | udelay(100); |
| 197 | if (timeout < 0) { |
| 198 | printf("ahci: Timeout during command execution.\n"); |
| 199 | return -1; |
| 200 | } |
| 201 | |
| 202 | ahci_prdbuf_finalize(dev); |
| 203 | |
| 204 | const u32 intr_status = ahci_clear_status(dev->port, intr_status); |
| 205 | if (intr_status & (HBA_PxIS_FATAL | HBA_PxIS_PCS)) { |
| 206 | ahci_error_recovery(dev, intr_status); |
| 207 | return -1; |
| 208 | } else { |
| 209 | return dev->cmdlist[slotnum].prd_bytes; |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | static size_t ahci_cmdslot_prepare(ahci_dev_t *const dev, |
| 214 | u8 *const user_buf, size_t buf_len, |
| 215 | const int out) |
| 216 | { |
| 217 | const int slotnum = 0; /* We always use the first slot. */ |
| 218 | |
| 219 | size_t read_count = 0; |
| 220 | |
| 221 | memset((void *)&dev->cmdlist[slotnum], |
| 222 | '\0', sizeof(dev->cmdlist[slotnum])); |
| 223 | memset((void *)dev->cmdtable, |
| 224 | '\0', sizeof(*dev->cmdtable)); |
| 225 | dev->cmdlist[slotnum].cmd = CMD_CFL(FIS_H2D_FIS_LEN); |
| 226 | dev->cmdlist[slotnum].cmdtable_base = virt_to_phys(dev->cmdtable); |
| 227 | |
| 228 | if (buf_len > 0) { |
| 229 | size_t prdt_len; |
| 230 | u8 *buf; |
| 231 | int i; |
| 232 | |
| 233 | prdt_len = ((buf_len - 1) >> BYTES_PER_PRD_SHIFT) + 1; |
| 234 | const size_t max_prdt_len = ARRAY_SIZE(dev->cmdtable->prdt); |
| 235 | if (prdt_len > max_prdt_len) { |
| 236 | prdt_len = max_prdt_len; |
| 237 | buf_len = prdt_len << BYTES_PER_PRD_SHIFT; |
| 238 | } |
| 239 | |
| 240 | dev->cmdlist[slotnum].prdt_length = prdt_len; |
| 241 | read_count = buf_len; |
| 242 | |
| 243 | buf = ahci_prdbuf_init(dev, user_buf, buf_len, out); |
| 244 | if (!buf) |
| 245 | return 0; |
| 246 | for (i = 0; i < prdt_len; ++i) { |
| 247 | const size_t bytes = |
| 248 | (buf_len < BYTES_PER_PRD) |
| 249 | ? buf_len : BYTES_PER_PRD; |
| 250 | dev->cmdtable->prdt[i].data_base = virt_to_phys(buf); |
| 251 | dev->cmdtable->prdt[i].flags = PRD_TABLE_BYTES(bytes); |
| 252 | buf_len -= bytes; |
| 253 | buf += bytes; |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | return read_count; |
| 258 | } |
| 259 | |
| 260 | static ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev, |
| 261 | const lba_t start, size_t count, |
| 262 | u8 *const buf) |
| 263 | { |
| 264 | ahci_dev_t *const dev = (ahci_dev_t *)ata_dev; |
| 265 | |
| 266 | if (count == 0) |
| 267 | return 0; |
| 268 | |
| 269 | if (ata_dev->read_cmd == ATA_READ_DMA) { |
| 270 | if (start >= (1 << 28)) { |
| 271 | printf("ahci: Sector is not 28-bit addressable.\n"); |
| 272 | return -1; |
| 273 | } else if (count > 256) { |
| 274 | printf("ahci: Sector count too high (max. 256).\n"); |
| 275 | count = 256; |
| 276 | } |
| 277 | #ifdef CONFIG_STORAGE_64BIT_LBA |
| 278 | } else if (ata_dev->read_cmd == ATA_READ_DMA_EXT) { |
| 279 | if (start >= (1ULL << 48)) { |
| 280 | printf("ahci: Sector is not 48-bit addressable.\n"); |
| 281 | return -1; |
| 282 | } else if (count > (64 * 1024)) { |
| 283 | printf("ahci: Sector count too high (max. 65536).\n"); |
| 284 | count = 64 * 1024; |
| 285 | } |
| 286 | #endif |
| 287 | } else { |
| 288 | printf("ahci: Unsupported ATA read command (0x%x).\n", |
| 289 | ata_dev->read_cmd); |
| 290 | return -1; |
| 291 | } |
| 292 | |
| 293 | const size_t bytes = count << ata_dev->sector_size_shift; |
| 294 | const size_t bytes_feasible = ahci_cmdslot_prepare(dev, buf, bytes, 0); |
| 295 | const size_t sectors = bytes_feasible >> ata_dev->sector_size_shift; |
| 296 | |
| 297 | dev->cmdtable->fis[ 0] = FIS_HOST_TO_DEVICE; |
| 298 | dev->cmdtable->fis[ 1] = FIS_H2D_CMD; |
| 299 | dev->cmdtable->fis[ 2] = ata_dev->read_cmd; |
| 300 | dev->cmdtable->fis[ 4] = (start >> 0) & 0xff; |
| 301 | dev->cmdtable->fis[ 5] = (start >> 8) & 0xff; |
| 302 | dev->cmdtable->fis[ 6] = (start >> 16) & 0xff; |
| 303 | dev->cmdtable->fis[ 7] = FIS_H2D_DEV_LBA; |
| 304 | dev->cmdtable->fis[ 8] = (start >> 24) & 0xff; |
| 305 | #ifdef CONFIG_STORAGE_64BIT_LBA |
| 306 | if (ata_dev->read_cmd == ATA_READ_DMA_EXT) { |
| 307 | dev->cmdtable->fis[ 9] = (start >> 32) & 0xff; |
| 308 | dev->cmdtable->fis[10] = (start >> 40) & 0xff; |
| 309 | } |
| 310 | #endif |
| 311 | dev->cmdtable->fis[12] = (sectors >> 0) & 0xff; |
| 312 | dev->cmdtable->fis[13] = (sectors >> 8) & 0xff; |
| 313 | |
| 314 | if (ahci_cmdslot_exec(dev) < 0) |
| 315 | return -1; |
| 316 | else |
| 317 | return dev->cmdlist->prd_bytes >> ata_dev->sector_size_shift; |
| 318 | } |
| 319 | |
| 320 | static ssize_t ahci_packet_read_cmd(atapi_dev_t *const _dev, |
| 321 | const u8 *const cmd, const size_t cmdlen, |
| 322 | u8 *const buf, const size_t buflen) |
| 323 | { |
| 324 | ahci_dev_t *const dev = (ahci_dev_t *)_dev; |
| 325 | |
| 326 | if ((cmdlen != 12) && (cmdlen != 16)) { |
| 327 | printf("ahci: Only 12- and 16-byte packet commands allowed.\n"); |
| 328 | return -1; |
| 329 | } |
| 330 | |
| 331 | const size_t len = ahci_cmdslot_prepare(dev, buf, buflen, 0); |
| 332 | u16 byte_limit = MIN(len, 63 * 1024); /* like Linux */ |
| 333 | if (byte_limit & 1) ++byte_limit; /* even limit */ |
| 334 | |
| 335 | dev->cmdlist[0].cmd |= CMD_ATAPI; |
| 336 | dev->cmdtable->fis[0] = FIS_HOST_TO_DEVICE; |
| 337 | dev->cmdtable->fis[1] = FIS_H2D_CMD; |
| 338 | dev->cmdtable->fis[2] = ATA_PACKET; |
| 339 | dev->cmdtable->fis[5] = byte_limit & 0xff; |
| 340 | dev->cmdtable->fis[6] = byte_limit >> 8; |
| 341 | memcpy((void *)dev->cmdtable->atapi_cmd, cmd, cmdlen); |
| 342 | |
| 343 | return ahci_cmdslot_exec(dev); |
| 344 | } |
| 345 | |
| 346 | static int ahci_identify_device(ata_dev_t *const ata_dev, u8 *const buf) |
| 347 | { |
| 348 | ahci_dev_t *const dev = (ahci_dev_t *)ata_dev; |
| 349 | |
| 350 | ahci_cmdslot_prepare(dev, buf, 512, 0); |
| 351 | |
| 352 | dev->cmdtable->fis[0] = FIS_HOST_TO_DEVICE; |
| 353 | dev->cmdtable->fis[1] = FIS_H2D_CMD; |
| 354 | dev->cmdtable->fis[2] = ata_dev->identify_cmd; |
| 355 | |
| 356 | if ((ahci_cmdslot_exec(dev) < 0) || (dev->cmdlist->prd_bytes != 512)) |
| 357 | return -1; |
| 358 | else |
| 359 | return 0; |
| 360 | } |
| 361 | |
| 362 | static int ahci_dev_init(hba_ctrl_t *const ctrl, |
| 363 | hba_port_t *const port, |
| 364 | const int portnum) |
| 365 | { |
| 366 | int ret = 1; |
| 367 | |
| 368 | const int ncs = HBA_CAPS_DECODE_NCS(ctrl->caps); |
| 369 | |
| 370 | /* Allocate command list, one command table and received FIS. */ |
| 371 | cmd_t *const cmdlist = memalign(1024, ncs * sizeof(cmd_t)); |
| 372 | cmdtable_t *const cmdtable = memalign(128, sizeof(cmdtable_t)); |
| 373 | rcvd_fis_t *const rcvd_fis = memalign(256, sizeof(rcvd_fis_t)); |
| 374 | /* Allocate our device structure. */ |
| 375 | ahci_dev_t *const dev = calloc(1, sizeof(ahci_dev_t)); |
| 376 | if (!cmdlist || !cmdtable || !rcvd_fis || !dev) |
| 377 | goto _cleanup_ret; |
| 378 | memset((void *)cmdlist, '\0', ncs * sizeof(cmd_t)); |
| 379 | memset((void *)cmdtable, '\0', sizeof(*cmdtable)); |
| 380 | memset((void *)rcvd_fis, '\0', sizeof(*rcvd_fis)); |
| 381 | |
| 382 | /* Set command list base and received FIS base. */ |
| 383 | if (ahci_cmdengine_stop(port)) |
| 384 | return 1; |
| 385 | port->cmdlist_base = virt_to_phys(cmdlist); |
| 386 | port->frameinfo_base = virt_to_phys(rcvd_fis); |
| 387 | if (ahci_cmdengine_start(port)) |
| 388 | return 1; |
| 389 | /* Put port into active state. */ |
| 390 | port->cmd_stat |= HBA_PxCMD_ICC_ACTIVE; |
| 391 | |
| 392 | dev->ctrl = ctrl; |
| 393 | dev->port = port; |
| 394 | dev->cmdlist = cmdlist; |
| 395 | dev->cmdtable = cmdtable; |
| 396 | dev->rcvd_fis = rcvd_fis; |
| 397 | |
| 398 | /* Wait for D2H Register FIS with device' signature. */ |
| 399 | int timeout = 200; /* Time out after 200 * 10ms == 2s. */ |
| 400 | while ((port->taskfile_data & HBA_PxTFD_BSY) && timeout--) |
| 401 | mdelay(10); |
| 402 | |
| 403 | /* Initialize device or fall through to clean up. */ |
| 404 | switch (port->signature) { |
| 405 | case HBA_PxSIG_ATA: |
| 406 | printf("ahci: ATA drive on port #%d.\n", portnum); |
| 407 | #ifdef CONFIG_STORAGE_ATA |
| 408 | dev->ata_dev.identify = ahci_identify_device; |
| 409 | dev->ata_dev.read_sectors = ahci_ata_read_sectors; |
| 410 | return ata_attach_device(&dev->ata_dev, PORT_TYPE_SATA); |
| 411 | #endif |
| 412 | break; |
| 413 | case HBA_PxSIG_ATAPI: |
| 414 | printf("ahci: ATAPI drive on port #%d.\n", portnum); |
| 415 | #ifdef CONFIG_STORAGE_ATAPI |
| 416 | dev->atapi_dev.identify = ahci_identify_device; |
| 417 | dev->atapi_dev.packet_read_cmd = ahci_packet_read_cmd; |
| 418 | return atapi_attach_device(&dev->atapi_dev, PORT_TYPE_SATA); |
| 419 | #endif |
| 420 | break; |
| 421 | default: |
| 422 | printf("ahci: Unsupported device (signature == 0x%08x) " |
| 423 | "on port #%d.\n", port->signature, portnum); |
| 424 | break; |
| 425 | } |
| 426 | ret = 2; |
| 427 | |
| 428 | _cleanup_ret: |
| 429 | /* Clean up (not reached for initialized devices). */ |
| 430 | if (dev) |
| 431 | free(dev); |
| 432 | if (!ahci_cmdengine_stop(port)) { |
| 433 | port->cmdlist_base = 0; |
| 434 | port->frameinfo_base = 0; |
| 435 | if (rcvd_fis) |
| 436 | free((void *)rcvd_fis); |
| 437 | if (cmdtable) |
| 438 | free((void *)cmdtable); |
| 439 | if (cmdlist) |
| 440 | free((void *)cmdlist); |
| 441 | } |
| 442 | return ret; |
| 443 | } |
| 444 | |
| 445 | static void ahci_port_probe(hba_ctrl_t *const ctrl, |
| 446 | hba_port_t *const port, |
| 447 | const int portnum) |
| 448 | { |
| 449 | /* If staggered spin-up is supported, spin-up device. */ |
| 450 | if (ctrl->caps & HBA_CAPS_SSS) { |
| 451 | port->cmd_stat |= HBA_PxCMD_SUD; |
| 452 | } |
| 453 | |
| 454 | /* Wait 1s if we just told the device to spin up or |
| 455 | if it's the first port. */ |
| 456 | if ((ctrl->caps & HBA_CAPS_SSS) || |
| 457 | !(ctrl->ports_impl & ((1 << (portnum - 1)) - 1))) { |
| 458 | /* Wait for port to become active. */ |
| 459 | int timeout = 100; /* Time out after 100 * 100us == 10ms. */ |
| 460 | while (!ahci_port_is_active(port) && timeout--) |
| 461 | udelay(100); |
| 462 | } |
| 463 | if (!ahci_port_is_active(port)) |
| 464 | return; |
| 465 | |
| 466 | ahci_clear_status(port, sata_error); |
| 467 | ahci_clear_status(port, intr_status); |
| 468 | |
| 469 | ahci_dev_init(ctrl, port, portnum); |
| 470 | } |
| 471 | |
| 472 | #ifdef CONFIG_STORAGE_AHCI_ONLY_TESTED |
| 473 | static u32 working_controllers[] = { |
| 474 | 0x8086 | 0x2929 << 16, |
| 475 | }; |
| 476 | #endif |
| 477 | static void ahci_init_pci(pcidev_t dev) |
| 478 | { |
| 479 | int i; |
| 480 | |
| 481 | const u16 class = pci_read_config16(dev, 0xa); |
| 482 | if (class != 0x0106) |
| 483 | return; |
| 484 | const u16 vendor = pci_read_config16(dev, 0x00); |
| 485 | const u16 device = pci_read_config16(dev, 0x02); |
| 486 | |
| 487 | #ifdef CONFIG_STORAGE_AHCI_ONLY_TESTED |
| 488 | const u32 vendor_device = pci_read_config32(dev, 0x0); |
| 489 | for (i = 0; i < ARRAY_SIZE(working_controllers); ++i) |
| 490 | if (vendor_device == working_controllers[i]) |
| 491 | break; |
| 492 | if (i == ARRAY_SIZE(working_controllers)) { |
| 493 | printf("ahci: Not using untested SATA controller " |
| 494 | "%02x:%02x.%02x (%04x:%04x).\n", PCI_BUS(dev), |
| 495 | PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); |
| 496 | return; |
| 497 | } |
| 498 | #endif |
| 499 | |
| 500 | printf("ahci: Found SATA controller %02x:%02x.%02x (%04x:%04x).\n", |
| 501 | PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); |
| 502 | |
| 503 | hba_ctrl_t *const ctrl = phys_to_virt( |
| 504 | pci_read_config32(dev, 0x24) & ~0x3ff); |
| 505 | hba_port_t *const ports = ctrl->ports; |
| 506 | |
| 507 | /* Reset host controller. */ |
| 508 | ctrl->global_ctrl |= HBA_CTRL_RESET; |
| 509 | /* Reset has to be finished after 1s. */ |
| 510 | delay(1); |
| 511 | if (ctrl->global_ctrl & HBA_CTRL_RESET) { |
| 512 | printf("ahci: ERROR: " |
| 513 | "Controller reset didn't finish within 1s.\n"); |
| 514 | return; |
| 515 | } |
| 516 | |
| 517 | /* Set AHCI access mode. */ |
| 518 | ctrl->global_ctrl |= HBA_CTRL_AHCI_EN; |
| 519 | |
| 520 | /* Probe for devices. */ |
| 521 | for (i = 0; i < 32; ++i) { |
| 522 | if (ctrl->ports_impl & (1 << i)) |
| 523 | ahci_port_probe(ctrl, &ports[i], i + 1); |
| 524 | } |
| 525 | } |
| 526 | |
| 527 | void ahci_initialize(void) |
| 528 | { |
| 529 | int bus, dev, func; |
| 530 | |
| 531 | for (bus = 0; bus < 256; ++bus) { |
| 532 | for (dev = 0; dev < 32; ++dev) { |
| 533 | const u16 class = |
| 534 | pci_read_config16(PCI_DEV(bus, dev, 0), 0xa); |
| 535 | if (class != 0xffff) { |
| 536 | for (func = 0; func < 8; ++func) |
| 537 | ahci_init_pci(PCI_DEV(bus, dev, func)); |
| 538 | } |
| 539 | } |
| 540 | } |
| 541 | } |