Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <device/pci_ops.h> |
| 23 | #include <cpu/x86/msr.h> |
| 24 | #include <cpu/amd/mtrr.h> |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 25 | #include <stdlib.h> |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 26 | #include <delay.h> |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 27 | #include <option.h> |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 28 | #include "sr5650.h" |
| 29 | #include "cmn.h" |
| 30 | |
| 31 | /* |
| 32 | * extern function declaration |
| 33 | */ |
| 34 | extern void set_pcie_dereset(void); |
| 35 | extern void set_pcie_reset(void); |
| 36 | |
| 37 | /* extension registers */ |
| 38 | u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) |
| 39 | { |
| 40 | /*get BAR3 base address for nbcfg0x1c */ |
| 41 | u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; |
| 42 | printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, |
| 43 | dev->path.pci.devfn); |
| 44 | addr |= dev->bus->secondary << 20 | /* bus num */ |
| 45 | dev->path.pci.devfn << 12 | reg; |
| 46 | return *((u32 *) addr); |
| 47 | } |
| 48 | |
| 49 | void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val) |
| 50 | { |
| 51 | u32 reg_old, reg; |
| 52 | |
| 53 | /*get BAR3 base address for nbcfg0x1c */ |
| 54 | u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; |
| 55 | /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, |
| 56 | dev->path.pci.devfn);*/ |
| 57 | addr |= dev->bus->secondary << 20 | /* bus num */ |
| 58 | dev->path.pci.devfn << 12 | reg_pos; |
| 59 | |
| 60 | reg = reg_old = *((u32 *) addr); |
| 61 | reg &= ~mask; |
| 62 | reg |= val; |
| 63 | if (reg != reg_old) { |
| 64 | *((u32 *) addr) = reg; |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | u32 nbpcie_p_read_index(device_t dev, u32 index) |
| 69 | { |
| 70 | return nb_read_index((dev), NBPCIE_INDEX, (index)); |
| 71 | } |
| 72 | |
| 73 | void nbpcie_p_write_index(device_t dev, u32 index, u32 data) |
| 74 | { |
| 75 | nb_write_index((dev), NBPCIE_INDEX, (index), (data)); |
| 76 | } |
| 77 | |
| 78 | u32 nbpcie_ind_read_index(device_t nb_dev, u32 index) |
| 79 | { |
| 80 | return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); |
| 81 | } |
| 82 | |
| 83 | void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data) |
| 84 | { |
| 85 | nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); |
| 86 | } |
| 87 | |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 88 | uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index) |
| 89 | { |
| 90 | return nb_read_index((nb_dev), L2CFG_INDEX, (index)); |
| 91 | } |
| 92 | |
| 93 | void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data) |
| 94 | { |
| 95 | nb_write_index((nb_dev), L2CFG_INDEX | (0x1 << 8), (index), (data)); |
| 96 | } |
| 97 | |
| 98 | uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index) |
| 99 | { |
| 100 | return nb_read_index((nb_dev), L1CFG_INDEX, (index)); |
| 101 | } |
| 102 | |
| 103 | void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data) |
| 104 | { |
| 105 | nb_write_index((nb_dev), L1CFG_INDEX | (0x1 << 31), (index), (data)); |
| 106 | } |
| 107 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 108 | /*********************************************************** |
| 109 | * To access bar3 we need to program PCI MMIO 7 in K8. |
| 110 | * in_out: |
| 111 | * 1: enable/enter k8 temp mmio base |
| 112 | * 0: disable/restore |
| 113 | ***********************************************************/ |
| 114 | void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) |
| 115 | { |
| 116 | /* K8 Function1 is address map */ |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 117 | device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); |
| 118 | device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 119 | |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 120 | if (in_out) { |
| 121 | u32 dword, sblk; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 122 | |
Timothy Pearson | c3fcdcc | 2015-09-05 17:46:38 -0500 | [diff] [blame] | 123 | /* Get SBLink value (HyperTransport I/O Hub Link ID). */ |
| 124 | dword = pci_read_config32(k8_f0, 0x64); |
| 125 | sblk = (dword >> 8) & 0x3; |
| 126 | |
| 127 | /* Fill MMIO limit/base pair. */ |
| 128 | pci_write_config32(k8_f1, 0xbc, |
| 129 | (((pcie_base_add + 0x10000000 - |
| 130 | 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); |
| 131 | pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); |
| 132 | pci_write_config32(k8_f1, 0xb4, |
| 133 | (((mmio_base_add + 0x10000000 - |
| 134 | 1) >> 8) & 0xffffff00) | (sblk << 4)); |
| 135 | pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); |
| 136 | } else { |
| 137 | pci_write_config32(k8_f1, 0xb8, 0); |
| 138 | pci_write_config32(k8_f1, 0xbc, 0); |
| 139 | pci_write_config32(k8_f1, 0xb0, 0); |
| 140 | pci_write_config32(k8_f1, 0xb4, 0); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 141 | } |
| 142 | } |
| 143 | |
| 144 | void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) |
| 145 | { |
| 146 | switch (port) { |
| 147 | case 2: /* GPP1, bit4-5 */ |
| 148 | case 3: |
| 149 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 150 | 1 << (port + 2), 0 << (port + 2)); |
| 151 | break; |
| 152 | case 4: /* GPP3a, bit20-24 */ |
| 153 | case 5: |
| 154 | case 6: |
| 155 | case 7: |
| 156 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 157 | 1 << (port + 17), 0 << (port + 17)); |
| 158 | break; |
| 159 | case 9: /* GPP3a, bit25,26 */ |
| 160 | case 10: |
| 161 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 162 | 1 << (port + 16), 0 << (port + 16)); |
| 163 | break; |
| 164 | case 11: /* GPP2, bit6-7 */ |
| 165 | case 12: |
| 166 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 167 | 1 << (port - 5), 0 << (port - 5)); |
| 168 | break; |
| 169 | case 13: /* GPP3b, bit4 of NBMISCIND:0x2A */ |
| 170 | set_nbmisc_enable_bits(nb_dev, 0x2A, |
| 171 | 1 << 4, 0 << 4); |
| 172 | break; |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | /******************************************************************************************************** |
| 177 | * Output: |
| 178 | * 0: no device is present. |
| 179 | * 1: device is present and is trained. |
| 180 | ********************************************************************************************************/ |
| 181 | u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) |
| 182 | { |
| 183 | u16 count = 5000; |
| 184 | u32 lc_state, reg, current_link_width, lane_mask; |
| 185 | u8 current, res = 0; |
| 186 | u32 gpp_sb_sel = 0; |
| 187 | |
| 188 | switch (port) { |
| 189 | case 2: |
| 190 | case 3: |
| 191 | gpp_sb_sel = PCIE_CORE_INDEX_GPP1; |
| 192 | break; |
| 193 | case 4 ... 7: |
| 194 | case 9: |
| 195 | case 10: |
| 196 | gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; |
| 197 | break; |
| 198 | case 11: |
| 199 | case 12: |
| 200 | gpp_sb_sel = PCIE_CORE_INDEX_GPP2; |
| 201 | break; |
| 202 | case 13: |
| 203 | gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; |
| 204 | break; |
| 205 | } |
| 206 | |
| 207 | while (count--) { |
| 208 | udelay(40200); |
| 209 | lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ |
| 210 | printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", |
| 211 | port, lc_state); |
| 212 | current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ |
| 213 | |
| 214 | switch (current) { |
| 215 | /* 0x00-0x04 means no device is present */ |
| 216 | case 0x06: |
| 217 | /* read back current link width [6:4]. */ |
| 218 | current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; |
| 219 | /* 4 means 7:4 and 15:12 |
| 220 | * 3 means 7:2 and 15:10 |
| 221 | * 2 means 7:1 and 15:9 |
Paul Menzel | 6a12109 | 2013-04-10 11:33:37 +0200 | [diff] [blame] | 222 | * ignoring the reversal case |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 223 | */ |
| 224 | lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; |
| 225 | reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel); |
| 226 | reg |= lane_mask << 8 | lane_mask; |
| 227 | /* NOTE: See the comments in rs780_pcie.c |
| 228 | * switching_gppsb_configurations |
| 229 | * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. |
| 230 | * But in this way, a x4 device in port B (dev 4) of |
| 231 | * Configuration B can only be detected as x1, instead |
| 232 | * of x4. When the port B is being trained, the |
| 233 | * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. |
| 234 | * We have to set the PCIEIND:0x65 as 0xE0E0 and reset |
| 235 | * the slot. Then the card seems to work in x1 mode. |
| 236 | */ |
| 237 | reg = 0xE0E0; /*I think that the lane_mask calc above is wrong, and this can't be hardcoded because the configuration changes.*/ |
| 238 | nbpcie_ind_write_index(nb_dev, 0x65 | gpp_sb_sel, reg); |
| 239 | printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", |
| 240 | current_link_width, lane_mask); |
| 241 | set_pcie_reset(); |
| 242 | mdelay(1); |
| 243 | set_pcie_dereset(); |
| 244 | break; |
| 245 | case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */ |
| 246 | res = 1; |
| 247 | count = 0; |
| 248 | break; |
| 249 | case 0x10: |
| 250 | reg = |
| 251 | pci_ext_read_config32(nb_dev, dev, |
| 252 | PCIE_VC0_RESOURCE_STATUS); |
| 253 | printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); |
| 254 | /* check bit1 */ |
| 255 | if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ |
| 256 | /* set bit8=1, bit0-2=bit4-6 */ |
| 257 | u32 tmp; |
Edward O'Callaghan | a9a2e10 | 2014-12-08 03:00:26 +1100 | [diff] [blame] | 258 | reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); |
| 259 | tmp = (reg >> 4) & 0x7; /* get bit4-6 */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 260 | reg &= 0xfff8; /* clear bit0-2 */ |
| 261 | reg += tmp; /* merge */ |
| 262 | reg |= 1 << 8; |
Edward O'Callaghan | a9a2e10 | 2014-12-08 03:00:26 +1100 | [diff] [blame] | 263 | nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 264 | count++; /* CIM said "keep in loop"? */ |
| 265 | } else { |
| 266 | res = 1; |
| 267 | count = 0; |
| 268 | } |
| 269 | break; |
| 270 | default: |
| 271 | /* CIMx Unknown Workaround - There is a device that won't train. Try to reset it. */ |
| 272 | /* if there are no device resets and nothing works, CIMx does a cf9 system reset (yikes!) */ |
| 273 | set_pcie_reset(); |
| 274 | mdelay(1); |
| 275 | set_pcie_dereset(); |
| 276 | res = 0; |
| 277 | count = 0; /* break loop */ |
| 278 | break; |
| 279 | } |
| 280 | } |
| 281 | return res; |
| 282 | } |
| 283 | |
| 284 | /* |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 285 | * Set Top Of Memory below and above 4G. |
| 286 | */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 287 | void sr5650_set_tom(device_t nb_dev) |
| 288 | { |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 289 | msr_t sysmem; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 290 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 291 | /* The system top memory in SR56X0. */ |
| 292 | sysmem = rdmsr(0xc001001A); |
| 293 | printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); |
| 294 | pci_write_config32(nb_dev, 0x90, sysmem.lo); |
| 295 | |
| 296 | sysmem = rdmsr(0xc001001D); |
| 297 | printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); |
| 298 | htiu_write_index(nb_dev, 0x31, sysmem.hi); |
| 299 | htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | u32 get_vid_did(device_t dev) |
| 303 | { |
| 304 | return pci_read_config32(dev, 0); |
| 305 | } |
| 306 | |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 307 | void detect_and_enable_iommu(device_t iommu_dev) { |
| 308 | uint32_t dword; |
| 309 | uint8_t l1_target; |
| 310 | unsigned char iommu; |
| 311 | void * mmio_base; |
| 312 | |
| 313 | iommu = 1; |
| 314 | get_option(&iommu, "iommu"); |
| 315 | |
| 316 | if (iommu) { |
| 317 | printk(BIOS_DEBUG, "Initializing IOMMU\n"); |
| 318 | |
| 319 | device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 320 | |
| 321 | if (!nb_dev) { |
| 322 | printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n"); |
| 323 | return; |
| 324 | } |
| 325 | |
| 326 | mmio_base = (void*)(pci_read_config32(iommu_dev, 0x44) & 0xffffc000); |
| 327 | |
| 328 | // if (get_nb_rev(nb_dev) == REV_SR5650_A11) { |
| 329 | // dword = pci_read_config32(iommu_dev, 0x6c); |
| 330 | // dword &= ~(0x1 << 8); |
| 331 | // pci_write_config32(iommu_dev, 0x6c, dword); |
| 332 | // } |
| 333 | |
| 334 | dword = pci_read_config32(iommu_dev, 0x50); |
| 335 | dword &= ~(0x1 << 22); |
| 336 | pci_write_config32(iommu_dev, 0x50, dword); |
| 337 | |
| 338 | dword = pci_read_config32(iommu_dev, 0x44); |
| 339 | dword |= 0x1; |
| 340 | pci_write_config32(iommu_dev, 0x44, dword); |
| 341 | |
| 342 | write32((void*)(mmio_base + 0x8), 0x0); |
| 343 | write32((void*)(mmio_base + 0xc), 0x08000000); |
| 344 | write32((void*)(mmio_base + 0x10), 0x0); |
| 345 | write32((void*)(mmio_base + 0x2008), 0x0); |
| 346 | write32((void*)(mmio_base + 0x2010), 0x0); |
| 347 | |
| 348 | /* IOMMU L1 initialization */ |
| 349 | for (l1_target = 0; l1_target < 6; l1_target++) { |
| 350 | dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0xc); |
| 351 | dword |= (0x7 << 28); |
| 352 | l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0xc, dword); |
| 353 | |
| 354 | dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0x7); |
| 355 | dword |= (0x1 << 5); |
| 356 | l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0x7, dword); |
| 357 | } |
| 358 | |
| 359 | /* IOMMU L2 initialization */ |
| 360 | dword = l2cfg_ind_read_index(nb_dev, 0xc); |
| 361 | dword |= (0x7 << 29); |
| 362 | l2cfg_ind_write_index(nb_dev, 0xc, dword); |
| 363 | |
| 364 | dword = l2cfg_ind_read_index(nb_dev, 0x10); |
| 365 | dword &= ~(0x3 << 8); |
| 366 | dword |= (0x2 << 8); |
| 367 | l2cfg_ind_write_index(nb_dev, 0x10, dword); |
| 368 | |
| 369 | dword = l2cfg_ind_read_index(nb_dev, 0x14); |
| 370 | dword &= ~(0x3 << 8); |
| 371 | dword |= (0x2 << 8); |
| 372 | l2cfg_ind_write_index(nb_dev, 0x14, dword); |
| 373 | |
| 374 | dword = l2cfg_ind_read_index(nb_dev, 0x18); |
| 375 | dword &= ~(0x3 << 8); |
| 376 | dword |= (0x2 << 8); |
| 377 | l2cfg_ind_write_index(nb_dev, 0x18, dword); |
| 378 | |
| 379 | dword = l2cfg_ind_read_index(nb_dev, 0x1c); |
| 380 | dword &= ~(0x3 << 8); |
| 381 | dword |= (0x2 << 8); |
| 382 | l2cfg_ind_write_index(nb_dev, 0x1c, dword); |
| 383 | |
| 384 | dword = l2cfg_ind_read_index(nb_dev, 0x50); |
| 385 | dword &= ~(0x3 << 8); |
| 386 | dword |= (0x2 << 8); |
| 387 | l2cfg_ind_write_index(nb_dev, 0x50, dword); |
| 388 | |
| 389 | dword = l2cfg_ind_read_index(nb_dev, 0x10); |
| 390 | dword |= (0x1 << 4); |
| 391 | l2cfg_ind_write_index(nb_dev, 0x10, dword); |
| 392 | |
| 393 | dword = l2cfg_ind_read_index(nb_dev, 0x14); |
| 394 | dword |= (0x1 << 4); |
| 395 | l2cfg_ind_write_index(nb_dev, 0x14, dword); |
| 396 | |
| 397 | dword = l2cfg_ind_read_index(nb_dev, 0x18); |
| 398 | dword |= (0x1 << 4); |
| 399 | l2cfg_ind_write_index(nb_dev, 0x18, dword); |
| 400 | |
| 401 | dword = l2cfg_ind_read_index(nb_dev, 0x1c); |
| 402 | dword |= (0x1 << 4); |
| 403 | l2cfg_ind_write_index(nb_dev, 0x1c, dword); |
| 404 | |
| 405 | dword = l2cfg_ind_read_index(nb_dev, 0x50); |
| 406 | dword |= (0x1 << 4); |
| 407 | l2cfg_ind_write_index(nb_dev, 0x50, dword); |
| 408 | |
| 409 | dword = l2cfg_ind_read_index(nb_dev, 0x6); |
| 410 | dword |= (0x1 << 7); |
| 411 | l2cfg_ind_write_index(nb_dev, 0x6, dword); |
| 412 | |
| 413 | dword = l2cfg_ind_read_index(nb_dev, 0x44); |
| 414 | dword |= (0x1 << 0); |
| 415 | l2cfg_ind_write_index(nb_dev, 0x44, dword); |
| 416 | |
| 417 | // if (get_nb_rev(nb_dev) == REV_SR5650_A21) { |
| 418 | dword = l2cfg_ind_read_index(nb_dev, 0x7); |
| 419 | dword |= (0x1 << 1); |
| 420 | l2cfg_ind_write_index(nb_dev, 0x7, dword); |
| 421 | |
| 422 | dword = l2cfg_ind_read_index(nb_dev, 0x44); |
| 423 | dword |= (0x1 << 1); |
| 424 | l2cfg_ind_write_index(nb_dev, 0x44, dword); |
| 425 | |
| 426 | dword = l2cfg_ind_read_index(nb_dev, 0x7); |
| 427 | dword |= (0x1 << 2); |
| 428 | l2cfg_ind_write_index(nb_dev, 0x7, dword); |
| 429 | |
| 430 | dword = l2cfg_ind_read_index(nb_dev, 0x7); |
| 431 | dword |= (0x1 << 3); |
| 432 | l2cfg_ind_write_index(nb_dev, 0x7, dword); |
| 433 | |
| 434 | dword = l2cfg_ind_read_index(nb_dev, 0x44); |
| 435 | dword |= (0x1 << 3); |
| 436 | l2cfg_ind_write_index(nb_dev, 0x44, dword); |
| 437 | |
| 438 | dword = l2cfg_ind_read_index(nb_dev, 0x7); |
| 439 | dword |= (0x1 << 4); |
| 440 | l2cfg_ind_write_index(nb_dev, 0x7, dword); |
| 441 | |
| 442 | dword = l2cfg_ind_read_index(nb_dev, 0x6); |
| 443 | dword |= (0x1 << 5); |
| 444 | l2cfg_ind_write_index(nb_dev, 0x6, dword); |
| 445 | |
| 446 | dword = l2cfg_ind_read_index(nb_dev, 0x6); |
| 447 | dword |= (0x1 << 6); |
| 448 | l2cfg_ind_write_index(nb_dev, 0x6, dword); |
| 449 | |
| 450 | dword = l2cfg_ind_read_index(nb_dev, 0x7); |
| 451 | dword |= (0x1 << 5); |
| 452 | l2cfg_ind_write_index(nb_dev, 0x7, dword); |
| 453 | |
| 454 | dword = l2cfg_ind_read_index(nb_dev, 0x44); |
| 455 | dword |= (0x1 << 4); |
| 456 | l2cfg_ind_write_index(nb_dev, 0x44, dword); |
| 457 | |
| 458 | dword = l2cfg_ind_read_index(nb_dev, 0x7); |
| 459 | dword |= (0x1 << 6); |
| 460 | l2cfg_ind_write_index(nb_dev, 0x7, dword); |
| 461 | |
| 462 | dword = l2cfg_ind_read_index(nb_dev, 0x7); |
| 463 | dword |= (0x1 << 7); |
| 464 | l2cfg_ind_write_index(nb_dev, 0x7, dword); |
| 465 | |
| 466 | dword = l2cfg_ind_read_index(nb_dev, 0x6); |
| 467 | dword |= (0x1 << 8); |
| 468 | l2cfg_ind_write_index(nb_dev, 0x6, dword); |
| 469 | // } |
| 470 | |
| 471 | l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002); |
| 472 | |
| 473 | dword = l2cfg_ind_read_index(nb_dev, 0x80); |
| 474 | dword |= (0x1 << 0); |
| 475 | l2cfg_ind_write_index(nb_dev, 0x80, dword); |
| 476 | |
| 477 | dword = l2cfg_ind_read_index(nb_dev, 0x30); |
| 478 | dword |= (0x1 << 0); |
| 479 | l2cfg_ind_write_index(nb_dev, 0x30, dword); |
| 480 | } |
| 481 | } |
| 482 | |
| 483 | void sr5650_iommu_read_resources(device_t dev) |
| 484 | { |
| 485 | unsigned char iommu; |
| 486 | struct resource *res; |
| 487 | |
| 488 | iommu = 1; |
| 489 | get_option(&iommu, "iommu"); |
| 490 | |
| 491 | /* Get the normal pci resources of this device */ |
| 492 | pci_dev_read_resources(dev); |
| 493 | |
| 494 | if (iommu) { |
| 495 | /* Request MMIO range allocation */ |
| 496 | res = new_resource(dev, 0x44); /* IOMMU */ |
| 497 | res->base = 0x0; |
| 498 | res->size = 0x4000; |
| 499 | res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ |
| 500 | res->align = 14; /* 16k alignment */ |
| 501 | res->gran = 14; |
| 502 | res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; |
| 503 | } |
| 504 | |
| 505 | compact_resources(dev); |
| 506 | } |
| 507 | |
| 508 | void sr5650_iommu_set_resources(device_t dev) |
| 509 | { |
| 510 | unsigned char iommu; |
| 511 | struct resource *res; |
| 512 | |
| 513 | iommu = 1; |
| 514 | get_option(&iommu, "iommu"); |
| 515 | |
| 516 | /* Get the normal pci resources of this device */ |
| 517 | pci_dev_read_resources(dev); |
| 518 | |
| 519 | if (iommu) { |
| 520 | /* Get the allocated range */ |
| 521 | res = find_resource(dev, 0x44); |
| 522 | |
| 523 | if (res->base == 0) { |
| 524 | printk(BIOS_WARNING, "Unable to allocate MMIO range to IOMMU\n"); |
| 525 | } |
| 526 | |
| 527 | /* Assign the range to hardware */ |
| 528 | pci_write_config32(dev, 0x44, res->base & 0xffffc000); |
| 529 | pci_write_config32(dev, 0x48, 0x0); |
| 530 | } |
| 531 | |
| 532 | /* Run standard resource set routine */ |
| 533 | pci_dev_set_resources(dev); |
| 534 | } |
| 535 | |
| 536 | void sr5650_iommu_enable_resources(device_t dev) |
| 537 | { |
| 538 | detect_and_enable_iommu(dev); |
| 539 | } |
| 540 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 541 | void sr5650_nb_pci_table(device_t nb_dev) |
| 542 | { /* NBPOR_InitPOR function. */ |
| 543 | u8 temp8; |
| 544 | u16 temp16; |
| 545 | u32 temp32; |
| 546 | |
| 547 | /* Program NB PCI table. */ |
| 548 | temp16 = pci_read_config16(nb_dev, 0x04); |
| 549 | printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); |
| 550 | temp32 = pci_read_config32(nb_dev, 0x84); |
| 551 | printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); |
| 552 | //Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge |
| 553 | //Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation |
| 554 | pci_write_config8(nb_dev, 0x4c, 0x42); |
| 555 | temp8 = pci_read_config8(nb_dev, 0x4e); |
| 556 | temp8 |= 0x05; /* BAR1_ENABLE */ |
| 557 | pci_write_config8(nb_dev, 0x4e, temp8); |
| 558 | |
| 559 | temp32 = pci_read_config32(nb_dev, 0x4c); |
| 560 | printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); |
| 561 | |
| 562 | /* disable GFX debug. */ |
| 563 | temp8 = pci_read_config8(nb_dev, 0x8d); |
| 564 | temp8 &= ~(1<<1); |
| 565 | pci_write_config8(nb_dev, 0x8d, temp8); |
| 566 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 567 | /* The system top memory in SR56X0. */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 568 | sr5650_set_tom(nb_dev); |
| 569 | |
| 570 | /* Program NB HTIU table. */ |
| 571 | //set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); |
| 572 | set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); |
| 573 | //set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); |
| 574 | set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); |
| 575 | set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); |
| 576 | set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); |
| 577 | set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); |
| 578 | set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); |
| 579 | set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); |
| 580 | } |
| 581 | |
| 582 | /*********************************************** |
| 583 | * 0:00.0 NBCFG : |
| 584 | * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default |
| 585 | * 0:01.0 P2P Internal: |
| 586 | * 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 587 | * 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 588 | * 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 589 | * 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 590 | * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 591 | * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 592 | * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 |
| 593 | * case 0 will be called twice, one is by cpu in hypertransport.c line458, |
| 594 | * the other is by sr5650. |
| 595 | ***********************************************/ |
| 596 | void sr5650_enable(device_t dev) |
| 597 | { |
| 598 | device_t nb_dev = 0, sb_dev = 0; |
| 599 | int dev_ind; |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 600 | struct southbridge_amd_sr5650_config *cfg; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 601 | |
| 602 | printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); |
| 603 | nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 604 | if (!nb_dev) { |
| 605 | die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n"); |
| 606 | /* NOT REACHED */ |
| 607 | } |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 608 | cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 609 | |
| 610 | /* sb_dev (dev 8) is a bridge that links to southbridge. */ |
| 611 | sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); |
| 612 | if (!sb_dev) { |
| 613 | die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n"); |
| 614 | /* NOT REACHED */ |
| 615 | } |
| 616 | |
| 617 | dev_ind = dev->path.pci.devfn >> 3; |
| 618 | switch (dev_ind) { |
| 619 | case 0: /* bus0, dev0, fun0; */ |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 620 | switch (dev->path.pci.devfn & 0x7) { |
| 621 | case 0: |
| 622 | printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); |
| 623 | enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 624 | |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 625 | config_gpp_core(nb_dev, sb_dev); |
| 626 | sr5650_gpp_sb_init(nb_dev, sb_dev, 8); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 627 | |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 628 | sr5650_nb_pci_table(nb_dev); |
| 629 | break; |
| 630 | case 1: |
| 631 | printk(BIOS_INFO, "Bus-0, Dev-0, Fun-1.\n"); |
| 632 | break; |
| 633 | case 2: |
| 634 | printk(BIOS_INFO, "Bus-0, Dev-0, Fun-2.\n"); |
| 635 | break; |
| 636 | } |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 637 | break; |
| 638 | |
| 639 | case 2: /* bus0, dev2,3 GPP1 */ |
| 640 | case 3: |
| 641 | printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); |
| 642 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
| 643 | (dev->enabled ? 0 : 1) << dev_ind); |
| 644 | if (dev->enabled) |
| 645 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); /* Note, dev 2,3 are generic PCIe ports. */ |
| 646 | break; |
| 647 | case 4: /* bus0, dev4-7, four GPP3a */ |
| 648 | case 5: |
| 649 | case 6: |
| 650 | case 7: |
| 651 | enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
| 652 | printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", |
| 653 | dev->enabled); |
| 654 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
| 655 | (dev->enabled ? 0 : 1) << dev_ind); |
| 656 | if (dev->enabled) |
| 657 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 658 | break; |
| 659 | case 8: /* bus0, dev8, SB */ |
| 660 | printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); |
| 661 | set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, |
| 662 | (dev->enabled ? 1 : 0) << 6); |
| 663 | if (dev->enabled) |
| 664 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 665 | disable_pcie_bar3(nb_dev); |
| 666 | break; |
| 667 | case 9: /* bus 0, dev 9,10, GPP3a */ |
| 668 | case 10: |
| 669 | printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", |
| 670 | dev->enabled); |
| 671 | enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
| 672 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
| 673 | (dev->enabled ? 0 : 1) << (7 + dev_ind)); |
| 674 | if (dev->enabled) |
| 675 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
Martin Roth | 55e31a9 | 2014-12-16 20:53:49 -0700 | [diff] [blame] | 676 | /* Don't call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 677 | break; |
| 678 | case 11: |
| 679 | case 12: /* bus 0, dev 11,12, GPP2 */ |
| 680 | printk(BIOS_INFO, "Bus-0, Dev-11,12, Fun-0. enable=%d\n", dev->enabled); |
| 681 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
| 682 | (dev->enabled ? 0 : 1) << (7 + dev_ind)); |
| 683 | if (dev->enabled) |
| 684 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 685 | break; |
| 686 | case 13: /* bus 0, dev 12, GPP3b */ |
| 687 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
| 688 | (dev->enabled ? 0 : 1) << (7 + dev_ind)); |
| 689 | if (dev->enabled) |
| 690 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 691 | break; |
| 692 | default: |
| 693 | printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); |
| 694 | } |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 695 | |
| 696 | /* Lock HWInit Register after the last device was done */ |
| 697 | if (dev_ind == 13) { |
| 698 | sr56x0_lock_hwinitreg(); |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 699 | udelay(cfg->pcie_settling_time); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 700 | } |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 701 | } |
| 702 | |
Timothy Pearson | 44e4a4e | 2015-08-11 17:49:06 -0500 | [diff] [blame] | 703 | static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length) |
| 704 | { |
| 705 | uint8_t *p; |
| 706 | struct device *sibling; |
| 707 | struct bus *link; |
| 708 | |
| 709 | if (!root_level) { |
| 710 | root_level = malloc(sizeof(int8_t)); |
| 711 | *root_level = -1; |
| 712 | } |
| 713 | |
| 714 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 715 | if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) |
| 716 | *root_level = depth; |
| 717 | |
| 718 | if (*root_level != -1) { |
| 719 | if (depth >= *root_level) { |
| 720 | if (dev->enabled) { |
| 721 | if (depth == *root_level) { |
| 722 | if (dev->path.pci.devfn < (0x1 << 3)) { |
| 723 | /* SR5690 control device */ |
| 724 | } else if ((dev->path.pci.devfn >= (0x1 << 3)) && (dev->path.pci.devfn < (0xe << 3))) { |
| 725 | /* SR5690 PCIe bridge device */ |
| 726 | } else { |
| 727 | if (dev->path.pci.devfn == (0x14 << 3)) { |
| 728 | /* SMBUS controller */ |
| 729 | p = (uint8_t *) *current; |
| 730 | p[0] = 0x2; /* Entry type */ |
| 731 | p[1] = dev->path.pci.devfn; /* Device */ |
| 732 | p[2] = dev->bus->secondary; /* Bus */ |
| 733 | p[3] = 0x97; /* Data */ |
| 734 | p[4] = 0x0; /* Padding */ |
| 735 | p[5] = 0x0; /* Padding */ |
| 736 | p[6] = 0x0; /* Padding */ |
| 737 | p[7] = 0x0; /* Padding */ |
| 738 | *length += 8; |
| 739 | *current += 8; |
| 740 | } else { |
| 741 | /* Other southbridge device */ |
| 742 | p = (uint8_t *) *current; |
| 743 | p[0] = 0x2; /* Entry type */ |
| 744 | p[1] = dev->path.pci.devfn; /* Device */ |
| 745 | p[2] = dev->bus->secondary; /* Bus */ |
| 746 | p[3] = 0x0; /* Data */ |
| 747 | p[4] = 0x0; /* Padding */ |
| 748 | p[5] = 0x0; /* Padding */ |
| 749 | p[6] = 0x0; /* Padding */ |
| 750 | p[7] = 0x0; /* Padding */ |
| 751 | *length += 8; |
| 752 | *current += 8; |
| 753 | } |
| 754 | } |
| 755 | } else { |
| 756 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { |
| 757 | /* Device behind bridge */ |
| 758 | if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { |
| 759 | /* Device is PCIe */ |
| 760 | p = (uint8_t *) *current; |
| 761 | p[0] = 0x2; /* Entry type */ |
| 762 | p[1] = dev->path.pci.devfn; /* Device */ |
| 763 | p[2] = dev->bus->secondary; /* Bus */ |
| 764 | p[3] = 0x0; /* Data */ |
| 765 | p[4] = 0x0; /* Padding */ |
| 766 | p[5] = 0x0; /* Padding */ |
| 767 | p[6] = 0x0; /* Padding */ |
| 768 | p[7] = 0x0; /* Padding */ |
| 769 | *length += 8; |
| 770 | *current += 8; |
| 771 | } else { |
| 772 | /* Device is legacy PCI or PCI-X */ |
| 773 | p = (uint8_t *) *current; |
| 774 | p[0] = 0x42; /* Entry type */ |
| 775 | p[1] = dev->path.pci.devfn; /* Device */ |
| 776 | p[2] = dev->bus->secondary; /* Bus */ |
| 777 | p[3] = 0x0; /* Data */ |
| 778 | p[4] = 0x0; /* Reserved */ |
| 779 | p[5] = parent->path.pci.devfn; /* Device */ |
| 780 | p[6] = parent->bus->secondary; /* Bus */ |
| 781 | p[7] = 0x0; /* Reserved */ |
| 782 | *length += 8; |
| 783 | *current += 8; |
| 784 | } |
| 785 | } |
| 786 | } |
| 787 | } |
| 788 | } |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | for (link = dev->link_list; link; link = link->next) |
| 793 | for (sibling = link->children; sibling; sibling = sibling->sibling) |
| 794 | add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); |
| 795 | |
| 796 | free(root_level); |
| 797 | } |
| 798 | |
| 799 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) |
| 800 | { |
| 801 | uint8_t *p; |
| 802 | |
| 803 | device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 804 | if (!nb_dev) { |
| 805 | printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 device! IVRS table not generated...\n"); |
| 806 | return (unsigned long)ivrs; |
| 807 | } |
| 808 | |
| 809 | device_t iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2)); |
| 810 | if (!iommu_dev) { |
| 811 | printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 IOMMU device! IVRS table not generated...\n"); |
| 812 | return (unsigned long)ivrs; |
| 813 | } |
| 814 | |
| 815 | ivrs->iv_info = 0x0; |
| 816 | ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */ |
| 817 | ivrs->iv_info |= (0x34 << 8); /* Maximum supported physical address size */ |
| 818 | |
| 819 | ivrs->ivhd.type = 0x10; |
| 820 | ivrs->ivhd.flags = 0x0e; |
| 821 | // if (get_nb_rev(nb_dev) != REV_SR5650_A11) { |
| 822 | ivrs->ivhd.flags |= 0x10; /* Enable ATS support on all revisions except A11 */ |
| 823 | // } |
| 824 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 825 | ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ |
| 826 | ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ |
| 827 | ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; |
| 828 | ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48); |
| 829 | ivrs->ivhd.pci_segment_group = 0x0; |
| 830 | ivrs->ivhd.iommu_info = 0x0; |
| 831 | ivrs->ivhd.iommu_info |= (0x14 << 8); |
| 832 | ivrs->ivhd.efr = 0x0; |
| 833 | |
| 834 | /* Describe HPET */ |
| 835 | p = (uint8_t *)current; |
| 836 | p[0] = 0x48; /* Entry type */ |
| 837 | p[1] = 0; /* Device */ |
| 838 | p[2] = 0; /* Bus */ |
| 839 | p[3] = 0xd7; /* Data */ |
| 840 | p[4] = 0x0; /* HPET number */ |
| 841 | p[5] = 0x14 << 3; /* HPET device */ |
| 842 | p[6] = nb_dev->bus->secondary; /* HPET bus */ |
| 843 | p[7] = 0x2; /* Variety */ |
| 844 | ivrs->ivhd.length += 8; |
| 845 | current += 8; |
| 846 | |
| 847 | /* Describe PCI devices */ |
| 848 | add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
| 849 | |
| 850 | /* Describe IOAPICs */ |
| 851 | unsigned long prev_current = current; |
| 852 | current = acpi_fill_ivrs_ioapic(ivrs, current); |
| 853 | ivrs->ivhd.length += (current - prev_current); |
| 854 | |
| 855 | return current; |
| 856 | } |
| 857 | |
| 858 | unsigned long southbridge_write_acpi_tables(device_t device, |
| 859 | unsigned long current, |
| 860 | struct acpi_rsdp *rsdp) |
| 861 | { |
| 862 | unsigned char iommu; |
| 863 | |
| 864 | iommu = 1; |
| 865 | get_option(&iommu, "iommu"); |
| 866 | |
| 867 | if (iommu) { |
| 868 | acpi_ivrs_t *ivrs; |
| 869 | |
| 870 | /* IVRS */ |
| 871 | current = ALIGN(current, 8); |
| 872 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 873 | ivrs = (acpi_ivrs_t *) current; |
| 874 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 875 | current += ivrs->header.length; |
| 876 | acpi_add_table(rsdp, ivrs); |
| 877 | } |
| 878 | |
| 879 | return current; |
| 880 | } |
| 881 | |
| 882 | static struct pci_operations iommu_ops_pci = { |
| 883 | .set_subsystem = pci_dev_set_subsystem, |
| 884 | }; |
| 885 | |
| 886 | static struct device_operations iommu_ops = { |
| 887 | .read_resources = sr5650_iommu_read_resources, |
| 888 | .set_resources = sr5650_iommu_set_resources, |
| 889 | .enable_resources = sr5650_iommu_enable_resources, |
| 890 | .write_acpi_tables = southbridge_write_acpi_tables, |
| 891 | .init = 0, |
| 892 | .scan_bus = 0, |
| 893 | .ops_pci = &iommu_ops_pci, |
| 894 | }; |
| 895 | |
| 896 | static const struct pci_driver ht_driver_sr5690 __pci_driver = { |
| 897 | .ops = &iommu_ops, |
| 898 | .vendor = PCI_VENDOR_ID_ATI, |
| 899 | .device = PCI_DEVICE_ID_AMD_SR5650_IOMMU, |
| 900 | }; |
| 901 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 902 | struct chip_operations southbridge_amd_sr5650_ops = { |
| 903 | CHIP_NAME("ATI SR5650") |
| 904 | .enable_dev = sr5650_enable, |
| 905 | }; |