Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
| 22 | #include <stddef.h> |
| 23 | #include <delay.h> |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 26 | #include <cbmem.h> |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 27 | #include <arch/cache.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 28 | #include "fimd.h" |
| 29 | #include "dp-core.h" |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 30 | #include "cpu.h" |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 31 | #include "clk.h" |
| 32 | #include "chip.h" |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 33 | |
David Hendricks | 0f5a3fc | 2013-03-12 20:16:44 -0700 | [diff] [blame] | 34 | #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) |
| 35 | #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 36 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 37 | static unsigned int cpu_id; |
| 38 | static unsigned int cpu_rev; |
| 39 | |
| 40 | static void set_cpu_id(void) |
| 41 | { |
| 42 | cpu_id = readl((void *)EXYNOS_PRO_ID); |
| 43 | cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12)); |
| 44 | |
| 45 | /* |
| 46 | * 0xC200: EXYNOS4210 EVT0 |
| 47 | * 0xC210: EXYNOS4210 EVT1 |
| 48 | */ |
| 49 | if (cpu_id == 0xC200) { |
| 50 | cpu_id |= 0x10; |
| 51 | cpu_rev = 0; |
| 52 | } else if (cpu_id == 0xC210) { |
| 53 | cpu_rev = 1; |
| 54 | } |
| 55 | } |
| 56 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 57 | /* we distinguish a display port device from a raw graphics device |
| 58 | * because there are dramatic differences in startup depending on |
| 59 | * graphics usage. To make startup fast and easier to understand and |
| 60 | * debug we explicitly name this common case. The alternate approach, |
| 61 | * involving lots of machine and callbacks, is hard to debug and |
| 62 | * verify. |
| 63 | */ |
| 64 | static void exynos_displayport_init(device_t dev) |
| 65 | { |
| 66 | int ret; |
| 67 | struct cpu_samsung_exynos5250_config *conf = dev->chip_info; |
| 68 | /* put these on the stack. If, at some point, we want to move |
| 69 | * this code to a pre-ram stage, it will be much easier. |
| 70 | */ |
| 71 | vidinfo_t vi; |
| 72 | struct exynos5_fimd_panel panel; |
| 73 | unsigned long int fb_size; |
| 74 | u32 lcdbase; |
| 75 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 76 | memset(&vi, 0, sizeof(vi)); |
| 77 | memset(&panel, 0, sizeof(panel)); |
| 78 | |
| 79 | panel.is_dp = 1; /* Display I/F is eDP */ |
| 80 | /* while it is true that we did a memset to zero, |
| 81 | * we leave some 'set to zero' entries here to make |
| 82 | * it clear what's going on. Graphics is confusing. |
| 83 | */ |
| 84 | panel.is_mipi = 0; |
| 85 | panel.fixvclk = 0; |
| 86 | panel.ivclk = 0; |
| 87 | panel.clkval_f = conf->clkval_f; |
| 88 | panel.upper_margin = conf->upper_margin; |
| 89 | panel.lower_margin = conf->lower_margin; |
| 90 | panel.vsync = conf->vsync; |
| 91 | panel.left_margin = conf->left_margin; |
| 92 | panel.right_margin = conf->right_margin; |
| 93 | panel.hsync = conf->hsync; |
Ronald G. Minnich | d83c117 | 2013-04-18 16:10:29 -0700 | [diff] [blame] | 94 | panel.xres = conf->xres; |
| 95 | panel.yres = conf->yres; |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 96 | |
| 97 | vi.vl_col = conf->xres; |
| 98 | vi.vl_row = conf->yres; |
| 99 | vi.vl_bpix = conf->bpp; |
| 100 | /* |
| 101 | * The size is a magic number from hardware. Allocate enough for the |
| 102 | * frame buffer and color map. |
| 103 | */ |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 104 | fb_size = conf->xres * conf->yres * (conf->bpp / 8); |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 105 | lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 106 | printk(BIOS_SPEW, "LCD colormap base is %p\n", (void *)(lcdbase)); |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 107 | mmio_resource(dev, 0, lcdbase/KiB, 64); |
| 108 | vi.cmap = (void *)lcdbase; |
| 109 | |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 110 | /* |
| 111 | * We need to clean and invalidate the framebuffer region and disable |
| 112 | * caching as well. We assume that our dcache <--> memory address |
| 113 | * space is identity-mapped in 1MB chunks, so align accordingly. |
| 114 | * |
| 115 | * Note: We may want to do something clever to ensure the framebuffer |
| 116 | * region is aligned such that we don't change dcache policy for other |
| 117 | * stuff inadvertantly. |
| 118 | * |
| 119 | * FIXME: Is disabling/re-enabling the MMU entirely necessary? |
| 120 | */ |
| 121 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
| 122 | uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB); |
| 123 | dcache_clean_invalidate_by_mva(lower, upper - lower); |
| 124 | dcache_mmu_disable(); |
| 125 | mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); |
| 126 | dcache_mmu_enable(); |
| 127 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 128 | lcdbase += 64*KiB; |
Ronald G. Minnich | e8a9134 | 2013-04-22 10:46:53 -0700 | [diff] [blame] | 129 | mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 130 | printk(BIOS_DEBUG, |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 131 | "Initializing Exynos VGA, base %p\n", (void *)lcdbase); |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 132 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 133 | ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); |
| 134 | } |
| 135 | |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 136 | static void cpu_init(device_t dev) |
| 137 | { |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 138 | exynos_displayport_init(dev); |
David Hendricks | 3cc0d1e | 2013-03-26 16:28:21 -0700 | [diff] [blame] | 139 | ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 140 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 141 | set_cpu_id(); |
| 142 | |
| 143 | printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", |
| 144 | cpu_id, get_arm_clk() / (1024*1024)); |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static void cpu_noop(device_t dev) |
| 148 | { |
| 149 | } |
| 150 | |
| 151 | static struct device_operations cpu_ops = { |
| 152 | .read_resources = cpu_noop, |
| 153 | .set_resources = cpu_noop, |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 154 | .enable_resources = cpu_init, |
| 155 | .init = cpu_noop, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 156 | .scan_bus = 0, |
| 157 | }; |
| 158 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 159 | static void enable_exynos5250_dev(device_t dev) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 160 | { |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 161 | dev->ops = &cpu_ops; |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | struct chip_operations cpu_samsung_exynos5250_ops = { |
| 165 | CHIP_NAME("CPU Samsung Exynos 5250") |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 166 | .enable_dev = enable_exynos5250_dev, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 167 | }; |
David Hendricks | c01d138 | 2013-03-28 19:04:58 -0700 | [diff] [blame] | 168 | |
| 169 | void exynos5250_config_l2_cache(void) |
| 170 | { |
| 171 | uint32_t val; |
| 172 | |
| 173 | /* |
| 174 | * Bit 9 - L2 tag RAM setup (1 cycle) |
| 175 | * Bits 8:6 - L2 tag RAM latency (3 cycles) |
| 176 | * Bit 5 - L2 data RAM setup (1 cycle) |
| 177 | * Bits 2:0 - L2 data RAM latency (3 cycles) |
| 178 | */ |
| 179 | val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); |
| 180 | write_l2ctlr(val); |
| 181 | } |