Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 2 | |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 2a27b20 | 2010-12-11 22:14:44 +0000 | [diff] [blame] | 7 | #include <cpu/intel/speedstep.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 8 | #include <cpu/x86/cache.h> |
Uwe Hermann | aac8f66 | 2010-09-29 09:54:16 +0000 | [diff] [blame] | 9 | #include <cpu/x86/name.h> |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 10 | |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 11 | #define HIGHEST_CLEVEL 3 |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 12 | static void configure_c_states(void) |
| 13 | { |
| 14 | msr_t msr; |
| 15 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 16 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 17 | msr.lo |= (1 << 15); // config lock until next reset |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 18 | msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 19 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 20 | msr.lo |= (1 << 3); // dynamic L2 |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 21 | |
| 22 | /* Number of supported C-States */ |
| 23 | msr.lo &= ~7; |
| 24 | msr.lo |= HIGHEST_CLEVEL; // support at most C3 |
| 25 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 26 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 27 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 28 | /* Set Processor MWAIT IO BASE (P_BLK) */ |
| 29 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 30 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) |
| 31 | << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 32 | wrmsr(MSR_PMG_IO_BASE_ADDR, msr); |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 33 | |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 34 | /* Set C_LVL controls and IO Capture Address */ |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 35 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 36 | // -2 because LVL0+1 aren't counted |
| 37 | msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 38 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 39 | } |
| 40 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 41 | static void configure_misc(void) |
| 42 | { |
| 43 | msr_t msr; |
| 44 | |
| 45 | msr = rdmsr(IA32_MISC_ENABLE); |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 46 | msr.lo |= (1 << 3); /* TM1 enable */ |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 47 | msr.lo |= (1 << 13); /* TM2 enable */ |
| 48 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
| 49 | |
| 50 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 51 | |
| 52 | // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 |
| 53 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 54 | |
Arthur Heymans | aacd548 | 2016-10-06 12:14:14 +0200 | [diff] [blame] | 55 | /* Enable C2E */ |
| 56 | msr.lo |= (1 << 26); |
| 57 | |
| 58 | /* Enable C4E */ |
| 59 | msr.hi |= (1 << (32 - 32)); // C4E |
| 60 | msr.hi |= (1 << (33 - 32)); // Hard C4E |
| 61 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 62 | wrmsr(IA32_MISC_ENABLE, msr); |
| 63 | |
| 64 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
| 65 | wrmsr(IA32_MISC_ENABLE, msr); |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 66 | |
| 67 | // set maximum CPU speed |
Elyes HAOUAS | 242ea84 | 2017-11-23 21:23:44 +0100 | [diff] [blame] | 68 | msr = rdmsr(IA32_PERF_STATUS); |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 69 | int busratio_max = (msr.hi >> (40-32)) & 0x1f; |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 70 | |
| 71 | msr = rdmsr(IA32_PLATFORM_ID); |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 72 | int vid_max = msr.lo & 0x3f; |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 73 | |
| 74 | msr.lo &= ~0xffff; |
| 75 | msr.lo |= busratio_max << 8; |
| 76 | msr.lo |= vid_max; |
| 77 | |
| 78 | wrmsr(IA32_PERF_CTL, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 79 | } |
| 80 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 81 | #define PIC_SENS_CFG 0x1aa |
| 82 | static void configure_pic_thermal_sensors(void) |
| 83 | { |
| 84 | msr_t msr; |
| 85 | |
| 86 | msr = rdmsr(PIC_SENS_CFG); |
| 87 | |
| 88 | msr.lo |= (1 << 21); // inter-core lock TM1 |
| 89 | msr.lo |= (1 << 4); // Enable bypass filter |
| 90 | |
| 91 | wrmsr(PIC_SENS_CFG, msr); |
| 92 | } |
| 93 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 94 | static void model_6ex_init(struct device *cpu) |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 95 | { |
| 96 | char processor_name[49]; |
| 97 | |
| 98 | /* Turn on caching if we haven't already */ |
Felix Held | 10796d8 | 2021-10-25 17:52:49 +0200 | [diff] [blame] | 99 | enable_cache(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 100 | |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 101 | /* Print processor name */ |
| 102 | fill_processor_name(processor_name); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 103 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 104 | |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 105 | /* Setup Page Attribute Tables (PAT) */ |
| 106 | // TODO set up PAT |
| 107 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 108 | /* Configure C States */ |
| 109 | configure_c_states(); |
| 110 | |
| 111 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 112 | configure_misc(); |
| 113 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 114 | /* PIC thermal sensor control */ |
| 115 | configure_pic_thermal_sensors(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | static struct device_operations cpu_dev_ops = { |
| 119 | .init = model_6ex_init, |
| 120 | }; |
| 121 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 122 | static const struct cpu_device_id cpu_table[] = { |
Felix Held | 6a6ac1e | 2023-02-06 15:19:11 +0100 | [diff] [blame] | 123 | { X86_VENDOR_INTEL, 0x06e0, CPUID_EXACT_MATCH_MASK }, /* Intel Core Solo/Core Duo */ |
| 124 | { X86_VENDOR_INTEL, 0x06e8, CPUID_EXACT_MATCH_MASK }, /* Intel Core Solo/Core Duo */ |
| 125 | { X86_VENDOR_INTEL, 0x06ec, CPUID_EXACT_MATCH_MASK }, /* Intel Core Solo/Core Duo */ |
Felix Held | 1e78165 | 2023-02-08 11:39:16 +0100 | [diff] [blame^] | 126 | CPU_TABLE_END |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | static const struct cpu_driver driver __cpu_driver = { |
| 130 | .ops = &cpu_dev_ops, |
| 131 | .id_table = cpu_table, |
| 132 | }; |