Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 2a27b20 | 2010-12-11 22:14:44 +0000 | [diff] [blame] | 7 | #include <cpu/intel/speedstep.h> |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 8 | #include <cpu/x86/cache.h> |
Uwe Hermann | aac8f66 | 2010-09-29 09:54:16 +0000 | [diff] [blame] | 9 | #include <cpu/x86/name.h> |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 10 | |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 11 | #define HIGHEST_CLEVEL 3 |
| 12 | static void configure_c_states(void) |
| 13 | { |
| 14 | msr_t msr; |
| 15 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 16 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 17 | msr.lo |= (1 << 15); // Lock configuration |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 18 | msr.lo |= (1 << 10); // redirect IO-based CState transition requests to |
| 19 | // MWAIT |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 20 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
| 21 | msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 |
| 22 | // TODO Do we want Deep C4 and Dynamic L2 shrinking? |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 23 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 24 | |
Stefan Reinauer | dfeb04d | 2010-12-12 00:37:41 +0000 | [diff] [blame] | 25 | /* Set Processor MWAIT IO BASE (P_BLK) */ |
| 26 | msr.hi = 0; |
| 27 | // TODO Do we want PM1_BASE? Needs SMM? |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 28 | //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) |
| 29 | // << 16); |
Stefan Reinauer | dfeb04d | 2010-12-12 00:37:41 +0000 | [diff] [blame] | 30 | msr.lo = ((PMB0_BASE + 4) & 0xffff); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 31 | wrmsr(MSR_PMG_IO_BASE_ADDR, msr); |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 32 | |
Stefan Reinauer | dfeb04d | 2010-12-12 00:37:41 +0000 | [diff] [blame] | 33 | /* set C_LVL controls */ |
| 34 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 35 | // -2 because LVL0+1 aren't counted |
| 36 | msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 37 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 38 | } |
| 39 | |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 40 | static void configure_misc(void) |
| 41 | { |
| 42 | msr_t msr; |
| 43 | |
| 44 | msr = rdmsr(IA32_MISC_ENABLE); |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 45 | msr.lo |= (1 << 3); /* TM1 enable */ |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 46 | msr.lo |= (1 << 13); /* TM2 enable */ |
| 47 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
| 48 | |
| 49 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 50 | |
| 51 | // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 |
| 52 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 53 | |
| 54 | // TODO Do we want Deep C4 and Dynamic L2 shrinking? |
| 55 | wrmsr(IA32_MISC_ENABLE, msr); |
| 56 | |
| 57 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
| 58 | wrmsr(IA32_MISC_ENABLE, msr); |
| 59 | } |
| 60 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 61 | static void model_106cx_init(struct device *cpu) |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 62 | { |
| 63 | char processor_name[49]; |
| 64 | |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 65 | /* Print processor name */ |
| 66 | fill_processor_name(processor_name); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 67 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 68 | |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 69 | /* Configure C States */ |
| 70 | configure_c_states(); |
| 71 | |
| 72 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 73 | configure_misc(); |
| 74 | |
| 75 | /* TODO: PIC thermal sensor control */ |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | static struct device_operations cpu_dev_ops = { |
Stefan Reinauer | 5fc7f98 | 2009-11-04 12:18:44 +0000 | [diff] [blame] | 79 | .init = model_106cx_init, |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 80 | }; |
| 81 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 82 | static const struct cpu_device_id cpu_table[] = { |
Felix Held | 6a6ac1e | 2023-02-06 15:19:11 +0100 | [diff] [blame] | 83 | { X86_VENDOR_INTEL, 0x106c0, CPUID_EXACT_MATCH_MASK }, /* Intel Atom 230 */ |
| 84 | { X86_VENDOR_INTEL, 0x106ca, CPUID_EXACT_MATCH_MASK }, /* Intel Atom D5xx */ |
Felix Held | 1e78165 | 2023-02-08 11:39:16 +0100 | [diff] [blame^] | 85 | CPU_TABLE_END |
Stefan Reinauer | 1a08f58 | 2009-10-28 16:52:48 +0000 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | static const struct cpu_driver driver __cpu_driver = { |
| 89 | .ops = &cpu_dev_ops, |
| 90 | .id_table = cpu_table, |
| 91 | }; |