blob: 00df880e977c7482f784df42c0ff0e8f654bc9d6 [file] [log] [blame]
Stefan Reinauereca92fb2006-08-23 14:28:37 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Stefan Reinauereca92fb2006-08-23 14:28:37 +00003 *
Uwe Hermannd82baa12006-12-05 14:13:10 +00004 * Copyright (C) 2000 AG Electronics Ltd.
5 * Copyright (C) 2003-2004 Linux Networx
Zheng Bao9db833b2009-12-28 09:59:44 +00006 * Copyright (C) 2004 Tyan
Stefan Reinauereca92fb2006-08-23 14:28:37 +00007 * Copyright (C) 2005 Digital Design Corporation
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Stefan Reinauereca92fb2006-08-23 14:28:37 +000018 */
Steven J. Magnanie91619a2005-09-12 18:55:23 +000019
Uwe Hermannd82baa12006-12-05 14:13:10 +000020/* RAM driver for SMSC LPC47B272 Super I/O chip. */
21
Steven J. Magnanie91619a2005-09-12 18:55:23 +000022#include <arch/io.h>
23#include <device/device.h>
24#include <device/pnp.h>
Nico Huber1c811282013-06-15 20:33:44 +020025#include <superio/conf_mode.h>
Steven J. Magnanie91619a2005-09-12 18:55:23 +000026#include <console/console.h>
27#include <device/smbus.h>
28#include <string.h>
Steven J. Magnanie91619a2005-09-12 18:55:23 +000029#include <pc80/keyboard.h>
Carl-Daniel Hailfinger2ee67792008-10-01 12:52:52 +000030#include <stdlib.h>
Steven J. Magnanie91619a2005-09-12 18:55:23 +000031#include "lpc47b272.h"
32
Edward O'Callaghan9e687a62015-01-04 16:35:43 +110033/**
34 * Initialize the specified Super I/O device.
35 *
36 * Devices other than COM ports and the keyboard controller are ignored.
37 * For COM ports, we configure the baud rate.
38 *
39 * @param dev Pointer to structure describing a Super I/O device.
40 */
41static void lpc47b272_init(struct device *dev)
42{
Steven J. Magnanie91619a2005-09-12 18:55:23 +000043
Edward O'Callaghan9e687a62015-01-04 16:35:43 +110044 if (!dev->enabled)
45 return;
46
47 switch(dev->path.pnp.device) {
48 case LPC47B272_KBC:
Timothy Pearson448e3862015-11-24 14:12:01 -060049 pc_keyboard_init(NO_AUX_DEVICE);
Edward O'Callaghan9e687a62015-01-04 16:35:43 +110050 break;
51 }
52}
Steven J. Magnanie91619a2005-09-12 18:55:23 +000053
54static struct device_operations ops = {
55 .read_resources = pnp_read_resources,
Nico Huber0b2ee932013-06-15 19:58:35 +020056 .set_resources = pnp_set_resources,
57 .enable_resources = pnp_enable_resources,
58 .enable = pnp_alt_enable,
Steven J. Magnanie91619a2005-09-12 18:55:23 +000059 .init = lpc47b272_init,
Nico Huber1c811282013-06-15 20:33:44 +020060 .ops_pnp_mode = &pnp_conf_mode_55_aa,
Steven J. Magnanie91619a2005-09-12 18:55:23 +000061};
62
63static struct pnp_info pnp_dev_info[] = {
Uwe Hermanna69d9782010-11-15 19:35:14 +000064 { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
65 { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
66 { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
67 { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
68 { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
69 { &ops, LPC47B272_RT, PNP_IO0, {0x0780, 0}, },
Steven J. Magnanie91619a2005-09-12 18:55:23 +000070};
71
Uwe Hermannb69cb5a2010-10-26 22:46:43 +000072/**
73 * Create device structures and allocate resources to devices specified in the
74 * pnp_dev_info array (above).
75 *
76 * @param dev Pointer to structure describing a Super I/O device.
Zheng Bao9db833b2009-12-28 09:59:44 +000077 */
Edward O'Callaghanf21bdc32014-10-21 07:43:41 +110078static void enable_dev(struct device *dev)
Stefan Reinauereca92fb2006-08-23 14:28:37 +000079{
Uwe Hermannb69cb5a2010-10-26 22:46:43 +000080 pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
Zheng Bao9db833b2009-12-28 09:59:44 +000081 pnp_dev_info);
Stefan Reinauereca92fb2006-08-23 14:28:37 +000082}
83
Edward O'Callaghan9e687a62015-01-04 16:35:43 +110084struct chip_operations superio_smsc_lpc47b272_ops = {
85 CHIP_NAME("SMSC LPC47B272 Super I/O")
86 .enable_dev = enable_dev
87};