blob: 8f8d137c55877c8012ba82b96eed25dd1f7a0685 [file] [log] [blame]
Nico Huberae7c9682013-05-23 18:13:23 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 secunet Security Networks AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Nico Huberae7c9682013-05-23 18:13:23 +020014 */
15
16/* =================== Generic PnP Device =================== */
17
18/*
19 * Generic setup for PnP devices.
20 *
21 * Controlled by the following preprocessor defines:
22 *
23 * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required)
24 * SUPERIO_PNP_LDN The logical device number on the super i/o
25 * chip for this device (required)
26 * SUPERIO_PNP_DDN A string literal that identifies the dos device
27 * name (DDN) of this device (e.g. "COM1", optional)
28 * SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down
29 * the logical device (optional)
Nico Huberdd94fa92013-07-01 16:29:16 +020030 * SUPERIO_PNP_PM_VAL The value for SUPERIO_PNP_PM_REG to power the logical
31 * device down (required if SUPERIO_PNP_PM_REG is defined)
Nico Huberae7c9682013-05-23 18:13:23 +020032 * SUPERIO_PNP_PM_LDN The logical device number to access the PM_REG
33 * bit (required if SUPERIO_PNP_PM_REG is defined)
34 * SUPERIO_PNP_IO0 The alignment and length of the first PnP i/o
35 * resource (comma seperated, e.g. `0x02, 0x08`,
36 * optional)
37 * SUPERIO_PNP_IO1 The alignment and length of the second PnP i/o
38 * resource (comma seperated, e.g. `0x02, 0x08`,
39 * optional)
40 * SUPERIO_PNP_IRQ0 If defined, the first PnP IRQ register is enabled
41 * SUPERIO_PNP_IRQ1 If defined, the second PnP IRQ register is enabled
42 * SUPERIO_PNP_DMA If defined, the PnP DMA register is enabled
43 */
44
45#include "pnp.asl"
46
47#ifndef SUPERIO_CHIP_NAME
48# error "SUPERIO_CHIP_NAME is not defined."
49#endif
50
51#ifndef SUPERIO_PNP_LDN
52# error "SUPERIO_PNP_LDN is not defined."
53#endif
54
55Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
56 Name (_HID, EisaId ("PNP0c02")) /* TODO: Better fitting EisaId? */
57 Name (_UID, SUPERIO_UID(PN, SUPERIO_PNP_LDN))
58 #ifdef SUPERIO_PNP_DDN
59 Name (_DDN, SUPERIO_PNP_DDN)
60 #endif
61
62 Method (_STA)
63 {
64 PNP_GENERIC_STA(SUPERIO_PNP_LDN)
65 }
66
67 Method (_DIS)
68 {
69 PNP_GENERIC_DIS(SUPERIO_PNP_LDN)
70 }
71
72#ifdef SUPERIO_PNP_PM_REG
73 Method (_PSC) {
Nico Huberdd94fa92013-07-01 16:29:16 +020074 PNP_GENERIC_PSC(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
Nico Huberae7c9682013-05-23 18:13:23 +020075 }
76
77 Method (_PS0) {
Nico Huberdd94fa92013-07-01 16:29:16 +020078 PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
Nico Huberae7c9682013-05-23 18:13:23 +020079 }
80
81 Method (_PS1) {
Nico Huberdd94fa92013-07-01 16:29:16 +020082 PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
Nico Huberae7c9682013-05-23 18:13:23 +020083 }
84#else
85 Method (_PSC) {
86 PNP_DEFAULT_PSC
87 }
88#endif
89
90 Method (_CRS)
91 {
92 Name (CRS, ResourceTemplate () {
93#ifdef SUPERIO_PNP_IO0
94 IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0)
95#endif
96#ifdef SUPERIO_PNP_IO1
97 IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
98#endif
99#ifdef SUPERIO_PNP_IRQ0
100 IRQNoFlags (IR0) {}
101#endif
102#ifdef SUPERIO_PNP_IRQ1
103 IRQNoFlags (IR1) {}
104#endif
105#ifdef SUPERIO_PNP_DMA
106 DMA (Compatibility, NotBusMaster, Transfer8, DM0) {}
107#endif
108 })
109 ENTER_CONFIG_MODE (SUPERIO_PNP_LDN)
110#ifdef SUPERIO_PNP_IO0
111 PNP_READ_IO(PNP_IO0, CRS, IO0)
112#endif
113#ifdef SUPERIO_PNP_IO1
114 PNP_READ_IO(PNP_IO1, CRS, IO1)
115#endif
116#ifdef SUPERIO_PNP_IRQ0
117 PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
118#endif
119#ifdef SUPERIO_PNP_IRQ1
120 PNP_READ_IRQ(PNP_IRQ1, CRS, IR1)
121#endif
122#ifdef SUPERIO_PNP_DMA
123 PNP_READ_DMA(PNP_DMA0, CRS, DM0)
124#endif
125 EXIT_CONFIG_MODE ()
126 Return (CRS)
127 }
128
129 Method (_SRS, 1, Serialized)
130 {
131 Name (TMPL, ResourceTemplate () {
132#ifdef SUPERIO_PNP_IO0
133 IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0)
134#endif
135#ifdef SUPERIO_PNP_IO1
136 IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
137#endif
138#ifdef SUPERIO_PNP_IRQ0
139 IRQNoFlags (IR0) {}
140#endif
141#ifdef SUPERIO_PNP_IRQ1
142 IRQNoFlags (IR1) {}
143#endif
144#ifdef SUPERIO_PNP_DMA
145 DMA (Compatibility, NotBusMaster, Transfer8, DM0) {}
146#endif
147 })
148 ENTER_CONFIG_MODE (SUPERIO_PNP_LDN)
149#ifdef SUPERIO_PNP_IO0
150 PNP_WRITE_IO(PNP_IO0, Arg0, IO0)
151#endif
152#ifdef SUPERIO_PNP_IO1
153 PNP_WRITE_IO(PNP_IO1, Arg0, IO1)
154#endif
155#ifdef SUPERIO_PNP_IRQ0
156 PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
157#endif
158#ifdef SUPERIO_PNP_IRQ1
159 PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1)
160#endif
161#ifdef SUPERIO_PNP_DMA
162 PNP_WRITE_DMA(PNP_DMA0, Arg0, DM0)
163#endif
164 Store (One, PNP_DEVICE_ACTIVE)
165 EXIT_CONFIG_MODE ()
166 }
167}