Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 4 | * Copyright (C) 2016-2017 Intel Corp. |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
Marshall Dawson | e8c527e | 2017-01-13 14:23:49 -0700 | [diff] [blame] | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #define __SIMPLE_DEVICE__ |
| 17 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 18 | #include <assert.h> |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 19 | #include <cpu/x86/mtrr.h> |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <soc/pci_devs.h> |
Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame] | 22 | #include <soc/ramstage.h> |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 23 | |
Lee Leahy | 7f4b053 | 2016-05-22 11:52:28 -0700 | [diff] [blame] | 24 | static uint16_t get_gpe0_address(uint32_t reg_address) |
| 25 | { |
| 26 | uint32_t gpe0_base_address; |
| 27 | |
| 28 | /* Get the GPE0 base address */ |
| 29 | gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK); |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 30 | ASSERT(gpe0_base_address >= 0x80000000); |
Lee Leahy | 7f4b053 | 2016-05-22 11:52:28 -0700 | [diff] [blame] | 31 | gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK; |
| 32 | |
| 33 | /* Return the GPE0 register address */ |
| 34 | return (uint16_t)(gpe0_base_address + reg_address); |
| 35 | } |
| 36 | |
Lee Leahy | ac690b1 | 2016-05-15 15:12:56 -0700 | [diff] [blame] | 37 | static uint32_t *get_gpio_address(uint32_t reg_address) |
| 38 | { |
| 39 | uint32_t gpio_base_address; |
| 40 | |
| 41 | /* Get the GPIO base address */ |
| 42 | gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1); |
| 43 | gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 44 | ASSERT(gpio_base_address != 0x00000000); |
Lee Leahy | ac690b1 | 2016-05-15 15:12:56 -0700 | [diff] [blame] | 45 | |
| 46 | /* Return the GPIO register address */ |
| 47 | return (uint32_t *)(gpio_base_address + reg_address); |
| 48 | } |
| 49 | |
| 50 | void *get_i2c_address(void) |
| 51 | { |
| 52 | uint32_t gpio_base_address; |
| 53 | |
| 54 | /* Get the GPIO base address */ |
| 55 | gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0); |
| 56 | gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 57 | ASSERT(gpio_base_address != 0x00000000); |
Lee Leahy | ac690b1 | 2016-05-15 15:12:56 -0700 | [diff] [blame] | 58 | |
| 59 | /* Return the GPIO register address */ |
| 60 | return (void *)gpio_base_address; |
| 61 | } |
| 62 | |
| 63 | static uint16_t get_legacy_gpio_address(uint32_t reg_address) |
| 64 | { |
| 65 | uint32_t gpio_base_address; |
| 66 | |
| 67 | /* Get the GPIO base address */ |
| 68 | gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE); |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 69 | ASSERT(gpio_base_address >= 0x80000000); |
Lee Leahy | ac690b1 | 2016-05-15 15:12:56 -0700 | [diff] [blame] | 70 | gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK; |
| 71 | |
| 72 | /* Return the GPIO register address */ |
| 73 | return (uint16_t)(gpio_base_address + reg_address); |
| 74 | } |
| 75 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 76 | static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) |
| 77 | { |
| 78 | uint32_t offset; |
| 79 | |
| 80 | /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */ |
| 81 | if (index == MTRR_CAP_MSR) |
| 82 | offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; |
| 83 | else if (index == MTRR_DEF_TYPE_MSR) |
| 84 | offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; |
| 85 | else if (index == MTRR_FIX_64K_00000) |
| 86 | offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; |
| 87 | else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) |
| 88 | offset = ((index - MTRR_FIX_16K_80000) << 1) |
| 89 | + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; |
| 90 | else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) |
| 91 | offset = ((index - MTRR_FIX_4K_C0000) << 1) |
| 92 | + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; |
| 93 | else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) |
| 94 | offset = (index - MTRR_PHYS_BASE(0)) |
| 95 | + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; |
| 96 | else { |
Lee Leahy | f74ce24 | 2016-07-31 17:20:30 -0700 | [diff] [blame] | 97 | printk(BIOS_SPEW, "index: 0x%08lx\n", index); |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 98 | die("Invalid MTRR index specified!\n"); |
| 99 | } |
| 100 | return offset; |
| 101 | } |
| 102 | |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 103 | void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) |
| 104 | { |
| 105 | pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, |
| 106 | (opcode << QNC_MCR_OP_OFFSET) |
| 107 | | ((uint32_t)port << QNC_MCR_PORT_OFFSET) |
| 108 | | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) |
| 109 | | QNC_MCR_BYTE_ENABLES); |
| 110 | } |
| 111 | |
| 112 | uint32_t mdr_read(void) |
| 113 | { |
| 114 | return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); |
| 115 | } |
| 116 | |
| 117 | void mdr_write(uint32_t value) |
| 118 | { |
| 119 | pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); |
| 120 | } |
| 121 | |
| 122 | void mea_write(uint32_t reg_address) |
| 123 | { |
| 124 | pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address |
| 125 | & QNC_MEA_MASK); |
| 126 | } |
| 127 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 128 | uint32_t port_reg_read(uint8_t port, uint32_t offset) |
| 129 | { |
| 130 | /* Read the port register */ |
| 131 | mea_write(offset); |
| 132 | mcr_write(QUARK_OPCODE_READ, port, offset); |
| 133 | return mdr_read(); |
| 134 | } |
| 135 | |
| 136 | void port_reg_write(uint8_t port, uint32_t offset, uint32_t value) |
| 137 | { |
| 138 | /* Write the port register */ |
| 139 | mea_write(offset); |
| 140 | mdr_write(value); |
| 141 | mcr_write(QUARK_OPCODE_WRITE, port, offset); |
| 142 | } |
| 143 | |
Lee Leahy | 5fafc6a | 2016-07-30 18:21:53 -0700 | [diff] [blame] | 144 | static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address) |
| 145 | { |
| 146 | /* Read the CPU CRx register */ |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 147 | switch (reg_address) { |
Lee Leahy | 5fafc6a | 2016-07-30 18:21:53 -0700 | [diff] [blame] | 148 | case 0: |
| 149 | return read_cr0(); |
| 150 | |
| 151 | case 4: |
| 152 | return read_cr4(); |
| 153 | } |
| 154 | die("ERROR - Unsupported CPU register!\n"); |
| 155 | } |
| 156 | |
| 157 | static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value) |
| 158 | { |
| 159 | /* Write the CPU CRx register */ |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 160 | switch (reg_address) { |
Lee Leahy | 5fafc6a | 2016-07-30 18:21:53 -0700 | [diff] [blame] | 161 | default: |
| 162 | die("ERROR - Unsupported CPU register!\n"); |
| 163 | |
| 164 | case 0: |
| 165 | write_cr0(value); |
Lee Leahy | d924fac | 2016-08-05 06:11:19 -0700 | [diff] [blame] | 166 | break; |
Lee Leahy | 5fafc6a | 2016-07-30 18:21:53 -0700 | [diff] [blame] | 167 | |
| 168 | case 4: |
| 169 | write_cr4(value); |
Lee Leahy | d924fac | 2016-08-05 06:11:19 -0700 | [diff] [blame] | 170 | break; |
Lee Leahy | 5fafc6a | 2016-07-30 18:21:53 -0700 | [diff] [blame] | 171 | } |
| 172 | } |
| 173 | |
Lee Leahy | 7f4b053 | 2016-05-22 11:52:28 -0700 | [diff] [blame] | 174 | static uint32_t reg_gpe0_read(uint32_t reg_address) |
| 175 | { |
| 176 | /* Read the GPE0 register */ |
| 177 | return inl(get_gpe0_address(reg_address)); |
| 178 | } |
| 179 | |
| 180 | static void reg_gpe0_write(uint32_t reg_address, uint32_t value) |
| 181 | { |
| 182 | /* Write the GPE0 register */ |
| 183 | outl(get_gpe0_address(reg_address), value); |
| 184 | } |
| 185 | |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 186 | static uint32_t reg_gpio_read(uint32_t reg_address) |
| 187 | { |
| 188 | /* Read the GPIO register */ |
| 189 | return *get_gpio_address(reg_address); |
| 190 | } |
| 191 | |
| 192 | static void reg_gpio_write(uint32_t reg_address, uint32_t value) |
| 193 | { |
| 194 | /* Write the GPIO register */ |
| 195 | *get_gpio_address(reg_address) = value; |
| 196 | } |
| 197 | |
Lee Leahy | 660c67a | 2016-07-10 17:09:24 -0700 | [diff] [blame] | 198 | uint32_t reg_host_bridge_unit_read(uint32_t reg_address) |
| 199 | { |
| 200 | /* Read the host bridge register */ |
| 201 | mea_write(reg_address); |
| 202 | mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, |
| 203 | reg_address); |
| 204 | return mdr_read(); |
| 205 | } |
| 206 | |
| 207 | static void reg_host_bridge_unit_write(uint32_t reg_address, uint32_t value) |
| 208 | { |
| 209 | /* Write the host bridge register */ |
| 210 | mea_write(reg_address); |
| 211 | mdr_write(value); |
| 212 | mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, |
| 213 | reg_address); |
| 214 | } |
| 215 | |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 216 | uint32_t reg_legacy_gpio_read(uint32_t reg_address) |
| 217 | { |
| 218 | /* Read the legacy GPIO register */ |
| 219 | return inl(get_legacy_gpio_address(reg_address)); |
| 220 | } |
| 221 | |
| 222 | void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value) |
| 223 | { |
| 224 | /* Write the legacy GPIO register */ |
| 225 | outl(value, get_legacy_gpio_address(reg_address)); |
| 226 | } |
| 227 | |
Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame] | 228 | static uint32_t reg_pcie_afe_read(uint32_t reg_address) |
| 229 | { |
| 230 | /* Read the PCIE AFE register */ |
| 231 | mea_write(reg_address); |
| 232 | mcr_write(QUARK_OPCODE_IO_READ, QUARK_SC_PCIE_AFE_SB_PORT_ID, |
| 233 | reg_address); |
| 234 | return mdr_read(); |
| 235 | } |
| 236 | |
| 237 | static void reg_pcie_afe_write(uint32_t reg_address, uint32_t value) |
| 238 | { |
| 239 | /* Write the PCIE AFE register */ |
| 240 | mea_write(reg_address); |
| 241 | mdr_write(value); |
| 242 | mcr_write(QUARK_OPCODE_IO_WRITE, QUARK_SC_PCIE_AFE_SB_PORT_ID, |
| 243 | reg_address); |
| 244 | } |
| 245 | |
Lee Leahy | 63e3dff | 2016-04-30 08:48:52 -0700 | [diff] [blame] | 246 | uint32_t reg_rmu_temp_read(uint32_t reg_address) |
| 247 | { |
| 248 | /* Read the RMU temperature register */ |
| 249 | mea_write(reg_address); |
| 250 | mcr_write(QUARK_OPCODE_READ, QUARK_NC_RMU_SB_PORT_ID, reg_address); |
| 251 | return mdr_read(); |
| 252 | } |
| 253 | |
| 254 | static void reg_rmu_temp_write(uint32_t reg_address, uint32_t value) |
| 255 | { |
| 256 | /* Write the RMU temperature register */ |
| 257 | mea_write(reg_address); |
| 258 | mdr_write(value); |
| 259 | mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_RMU_SB_PORT_ID, reg_address); |
| 260 | } |
| 261 | |
| 262 | static uint32_t reg_soc_unit_read(uint32_t reg_address) |
| 263 | { |
| 264 | /* Read the temperature sensor register */ |
| 265 | mea_write(reg_address); |
| 266 | mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, |
| 267 | reg_address); |
| 268 | return mdr_read(); |
| 269 | } |
| 270 | |
| 271 | static void reg_soc_unit_write(uint32_t reg_address, uint32_t value) |
| 272 | { |
| 273 | /* Write the temperature sensor register */ |
| 274 | mea_write(reg_address); |
| 275 | mdr_write(value); |
| 276 | mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SCSS_SOC_UNIT_SB_PORT_ID, |
| 277 | reg_address); |
| 278 | } |
| 279 | |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 280 | static uint32_t reg_usb_read(uint32_t reg_address) |
| 281 | { |
| 282 | /* Read the USB register */ |
| 283 | mea_write(reg_address); |
| 284 | mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SC_USB_AFE_SB_PORT_ID, |
| 285 | reg_address); |
| 286 | return mdr_read(); |
| 287 | } |
| 288 | |
| 289 | static void reg_usb_write(uint32_t reg_address, uint32_t value) |
| 290 | { |
| 291 | /* Write the USB register */ |
| 292 | mea_write(reg_address); |
| 293 | mdr_write(value); |
| 294 | mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SC_USB_AFE_SB_PORT_ID, |
| 295 | reg_address); |
| 296 | } |
| 297 | |
| 298 | static uint64_t reg_read(struct reg_script_context *ctx) |
| 299 | { |
| 300 | const struct reg_script *step = ctx->step; |
| 301 | uint64_t value = 0; |
| 302 | |
| 303 | switch (step->id) { |
| 304 | default: |
| 305 | printk(BIOS_ERR, |
| 306 | "ERROR - Unknown register set (0x%08x)!\n", |
| 307 | step->id); |
| 308 | ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; |
| 309 | return 0; |
| 310 | |
Lee Leahy | 5fafc6a | 2016-07-30 18:21:53 -0700 | [diff] [blame] | 311 | case CPU_CR: |
| 312 | ctx->display_prefix = "CPU CR"; |
| 313 | value = reg_cpu_cr_read(step->reg); |
| 314 | break; |
| 315 | |
Lee Leahy | 7f4b053 | 2016-05-22 11:52:28 -0700 | [diff] [blame] | 316 | case GPE0_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 317 | ctx->display_prefix = "GPE0"; |
Lee Leahy | 7f4b053 | 2016-05-22 11:52:28 -0700 | [diff] [blame] | 318 | value = reg_gpe0_read(step->reg); |
| 319 | break; |
| 320 | |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 321 | case GPIO_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 322 | ctx->display_prefix = "GPIO"; |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 323 | value = reg_gpio_read(step->reg); |
| 324 | break; |
| 325 | |
Lee Leahy | 660c67a | 2016-07-10 17:09:24 -0700 | [diff] [blame] | 326 | case HOST_BRIDGE: |
| 327 | ctx->display_prefix = "Host Bridge"; |
| 328 | value = reg_host_bridge_unit_read(step->reg); |
| 329 | break; |
| 330 | |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 331 | case LEG_GPIO_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 332 | ctx->display_prefix = "Legacy GPIO"; |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 333 | value = reg_legacy_gpio_read(step->reg); |
Lee Leahy | b0672402 | 2016-07-18 10:39:55 -0700 | [diff] [blame] | 334 | break; |
Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame] | 335 | |
| 336 | case PCIE_AFE_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 337 | ctx->display_prefix = "PCIe AFE"; |
Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame] | 338 | value = reg_pcie_afe_read(step->reg); |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 339 | break; |
| 340 | |
Lee Leahy | 63e3dff | 2016-04-30 08:48:52 -0700 | [diff] [blame] | 341 | case RMU_TEMP_REGS: |
| 342 | ctx->display_prefix = "RMU TEMP"; |
| 343 | value = reg_rmu_temp_read(step->reg); |
| 344 | break; |
| 345 | |
| 346 | case SOC_UNIT_REGS: |
| 347 | ctx->display_prefix = "SOC Unit"; |
| 348 | value = reg_soc_unit_read(step->reg); |
| 349 | break; |
| 350 | |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 351 | case USB_PHY_REGS: |
| 352 | ctx->display_prefix = "USB PHY"; |
| 353 | value = reg_usb_read(step->reg); |
| 354 | break; |
| 355 | } |
| 356 | return value; |
| 357 | } |
| 358 | |
| 359 | static void reg_write(struct reg_script_context *ctx) |
| 360 | { |
| 361 | const struct reg_script *step = ctx->step; |
| 362 | |
| 363 | switch (step->id) { |
| 364 | default: |
| 365 | printk(BIOS_ERR, |
| 366 | "ERROR - Unknown register set (0x%08x)!\n", |
| 367 | step->id); |
| 368 | ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; |
| 369 | return; |
| 370 | |
Lee Leahy | 5fafc6a | 2016-07-30 18:21:53 -0700 | [diff] [blame] | 371 | case CPU_CR: |
| 372 | ctx->display_prefix = "CPU CR"; |
| 373 | reg_cpu_cr_write(step->reg, step->value); |
| 374 | break; |
| 375 | |
Lee Leahy | 7f4b053 | 2016-05-22 11:52:28 -0700 | [diff] [blame] | 376 | case GPE0_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 377 | ctx->display_prefix = "GPE0"; |
Lee Leahy | 7f4b053 | 2016-05-22 11:52:28 -0700 | [diff] [blame] | 378 | reg_gpe0_write(step->reg, (uint32_t)step->value); |
| 379 | break; |
| 380 | |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 381 | case GPIO_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 382 | ctx->display_prefix = "GPIO"; |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 383 | reg_gpio_write(step->reg, (uint32_t)step->value); |
| 384 | break; |
| 385 | |
Lee Leahy | 660c67a | 2016-07-10 17:09:24 -0700 | [diff] [blame] | 386 | case HOST_BRIDGE: |
| 387 | ctx->display_prefix = "Host Bridge"; |
| 388 | reg_host_bridge_unit_write(step->reg, (uint32_t)step->value); |
| 389 | break; |
| 390 | |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 391 | case LEG_GPIO_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 392 | ctx->display_prefix = "Legacy GPIO"; |
Lee Leahy | 083da16 | 2016-05-15 13:32:24 -0700 | [diff] [blame] | 393 | reg_legacy_gpio_write(step->reg, (uint32_t)step->value); |
| 394 | break; |
| 395 | |
Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame] | 396 | case PCIE_AFE_REGS: |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 397 | ctx->display_prefix = "PCIe AFE"; |
Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame] | 398 | reg_pcie_afe_write(step->reg, (uint32_t)step->value); |
| 399 | break; |
| 400 | |
| 401 | case PCIE_RESET: |
| 402 | if (ctx->display_features) { |
Lee Leahy | 6b24dfc | 2016-05-22 16:24:36 -0700 | [diff] [blame] | 403 | ctx->display_prefix = "PCIe reset"; |
Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame] | 404 | ctx->display_features &= ~REG_SCRIPT_DISPLAY_REGISTER; |
| 405 | } |
| 406 | mainboard_gpio_pcie_reset(step->value); |
| 407 | break; |
| 408 | |
Lee Leahy | 63e3dff | 2016-04-30 08:48:52 -0700 | [diff] [blame] | 409 | case RMU_TEMP_REGS: |
| 410 | ctx->display_prefix = "RMU TEMP"; |
| 411 | reg_rmu_temp_write(step->reg, (uint32_t)step->value); |
| 412 | break; |
| 413 | |
| 414 | case SOC_UNIT_REGS: |
| 415 | ctx->display_prefix = "SOC Unit"; |
| 416 | reg_soc_unit_write(step->reg, (uint32_t)step->value); |
| 417 | break; |
| 418 | |
Lee Leahy | 4c3f5dc | 2016-04-29 16:36:02 -0700 | [diff] [blame] | 419 | case MICROSECOND_DELAY: |
| 420 | /* The actual delay is >= the requested delay */ |
| 421 | if (ctx->display_features) { |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 422 | /* Higher baud-rates will reduce the impact of |
| 423 | * displaying this message |
| 424 | */ |
Lee Leahy | 4c3f5dc | 2016-04-29 16:36:02 -0700 | [diff] [blame] | 425 | printk(BIOS_INFO, "Delay %lld uSec\n", step->value); |
| 426 | ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; |
| 427 | } |
| 428 | udelay(step->value); |
| 429 | break; |
| 430 | |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 431 | case USB_PHY_REGS: |
| 432 | ctx->display_prefix = "USB PHY"; |
| 433 | reg_usb_write(step->reg, (uint32_t)step->value); |
| 434 | break; |
| 435 | } |
| 436 | } |
| 437 | |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 438 | msr_t soc_msr_read(unsigned int index) |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 439 | { |
| 440 | uint32_t offset; |
| 441 | union { |
| 442 | uint64_t u64; |
| 443 | msr_t msr; |
| 444 | } value; |
| 445 | |
| 446 | /* Read the low 32-bits of the register */ |
| 447 | offset = mtrr_index_to_host_bridge_register_offset(index); |
| 448 | value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); |
| 449 | |
| 450 | /* For 64-bit registers, read the upper 32-bits */ |
| 451 | if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) |
| 452 | && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { |
| 453 | offset += 1; |
| 454 | value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, |
| 455 | offset); |
| 456 | } |
| 457 | return value.msr; |
| 458 | } |
| 459 | |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 460 | void soc_msr_write(unsigned int index, msr_t msr) |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 461 | { |
| 462 | uint32_t offset; |
| 463 | union { |
| 464 | uint32_t u32[2]; |
| 465 | msr_t msr; |
| 466 | } value; |
| 467 | |
| 468 | /* Write the low 32-bits of the register */ |
| 469 | value.msr = msr; |
| 470 | offset = mtrr_index_to_host_bridge_register_offset(index); |
| 471 | port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]); |
| 472 | |
| 473 | /* For 64-bit registers, write the upper 32-bits */ |
| 474 | if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) |
| 475 | && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { |
| 476 | offset += 1; |
| 477 | port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, |
| 478 | value.u32[1]); |
| 479 | } |
| 480 | } |
| 481 | |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 482 | const struct reg_script_bus_entry soc_reg_script_bus_table = { |
| 483 | SOC_TYPE, reg_read, reg_write |
| 484 | }; |
| 485 | |
| 486 | REG_SCRIPT_BUS_ENTRY(soc_reg_script_bus_table); |