| Brenton Dong | c9b3981 | 2016-10-18 13:57:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <cpu/x86/mtrr.h> |
| 18 | #include <cpu/x86/cr.h> |
| 19 | #include <soc/cpu.h> |
| 20 | |
| 21 | /* |
| 22 | * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. |
| 23 | * This version of chipset_teardown_car sets up the stack, then bypasses |
| 24 | * the rest of arch/x86/exit_car.S and calls main() itself instead of |
| 25 | * returning to _start. In main(), the TempRamExit FSP API is called |
| 26 | * to tear down the CAR and set up caching which can be overwritten |
| 27 | * after the API call. More info can be found in the Apollo Lake FSP |
| 28 | * Integration Guide included with the FSP binary. The below |
| 29 | * caching settings are based on an 8MiB Flash Size given as a |
| 30 | * parameter to TempRamInit. |
| 31 | * |
| 32 | * TempRamExit MTRR Settings: |
| 33 | * 0x00000000 - 0x0009FFFF | Write Back |
| 34 | * 0x000C0000 - Top of Low Memory | Write Back |
| 35 | * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect |
| 36 | * 0x100000000 - Top of High Memory | Write Back |
| 37 | */ |
| 38 | |
| 39 | .text |
| 40 | .global chipset_teardown_car |
| 41 | chipset_teardown_car: |
| 42 | |
| 43 | /* Set up new stack. */ |
| 44 | mov post_car_stack_top, %esp |
| 45 | |
| 46 | /* Call C code */ |
| 47 | call main |