blob: 7219b0b397ff22d6c33b1ed92ecfd1d23a640db4 [file] [log] [blame]
Dennis Wassenbergbd105162015-09-10 12:20:58 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <northbridge/intel/sandybridge/sandybridge.h>
17#include <southbridge/intel/bd82x6x/pch.h>
18
19void rcba_config(void)
20{
21 u32 reg32;
22
23 /* Disable unused devices (board specific) */
24 reg32 = RCBA32(FD);
25 reg32 |= PCH_DISABLE_ALWAYS;
26 /* Disable PCI bridge so MRC does not probe this bus */
27 reg32 |= PCH_DISABLE_P2P;
28 RCBA32(FD) = reg32;
29}
30
31void mainboard_early_init(int s3resume)
32{
33}
34
35int mainboard_should_reset_usb(int s3resume)
36{
37 return !s3resume;
38}