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review.coreboot.org / coreboot / 1e24bf3f719f82c16fd577e87900e1aa0fd6605b / . / src / mainboard / hp / abm / buildOpts.c
blob: 2f31c5e8040ea2e65768263689763833e39ff1df [file] [log] [blame]
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
Dave Frodin83405a12014-06-05 11:49:04 -0600[diff] [blame]5 * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]15 */
16
17/**
18 * @file
19 *
20 * AMD User options selection for a Brazos platform solution system
21 *
22 * This file is placed in the user's platform directory and contains the
23 * build option selections desired for that platform.
24 *
25 * For Information about this file, see @ref platforminstall.
26 *
27 * @xrefitem bom "File Content Label" "Release Content"
28 * @e project: AGESA
29 * @e sub-project: Core
30 * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
31 */
32
33#include <stdlib.h>
34#include "AGESA.h"
35#include "Filecode.h"
36#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
37
38#define INSTALL_FT3_SOCKET_SUPPORT TRUE
39#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
40
41#define INSTALL_G34_SOCKET_SUPPORT FALSE
42#define INSTALL_C32_SOCKET_SUPPORT FALSE
43#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
44#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
45#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
46#define INSTALL_FS1_SOCKET_SUPPORT FALSE
47#define INSTALL_FM1_SOCKET_SUPPORT FALSE
48#define INSTALL_FP2_SOCKET_SUPPORT FALSE
49#define INSTALL_FT1_SOCKET_SUPPORT FALSE
50#define INSTALL_AM3_SOCKET_SUPPORT FALSE
51#define INSTALL_FM2_SOCKET_SUPPORT FALSE
52
53
54#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
55 #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
56 #undef INSTALL_FT3_SOCKET_SUPPORT
57 #define INSTALL_FT3_SOCKET_SUPPORT FALSE
58 #endif
59#endif
60
61//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
62//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
63#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
64//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
65//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
66//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
67#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
68#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
69#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
70//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
71#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
72//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
73#define BLDOPT_REMOVE_SRAT FALSE //TRUE
74#define BLDOPT_REMOVE_SLIT FALSE //TRUE
75#define BLDOPT_REMOVE_WHEA FALSE //TRUE
Dave Frodin83405a12014-06-05 11:49:04 -0600[diff] [blame]76#define BLDOPT_REMOVE_CRAT TRUE
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]77#define BLDOPT_REMOVE_CDIT TRUE
78#define BLDOPT_REMOVE_DMI TRUE
79//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
80//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
81//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
82//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
83//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
84//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
85
86//This element selects whether P-States should be forced to be independent,
87// as reported by the ACPI _PSD object. For single-link processors,
88// setting TRUE for OS to support this feature.
89
90//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
91
92#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
93#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
94/* Build configuration values here.
95 */
96#define BLDCFG_VRM_CURRENT_LIMIT 15000
97#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
98#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
99#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
100#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
101#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
102#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
103#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
104#define BLDCFG_VRM_SLEW_RATE 10000
105#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
106#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
107
108#define BLDCFG_PLAT_NUM_IO_APICS 3
109#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
110#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
111#define BLDCFG_MEM_INIT_PSTATE 0
112#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
113 // core for C-state entry requests. A value
114 // of 0 in this field specifies that the core
115 // does not trap any IO addresses for C-state entry.
116 // Values greater than 0xFFF8 results in undefined behavior.
117#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
118
119#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
120
121#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
122#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
123#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
124#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
125#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
126#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
127#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
128#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
129#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
130#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
131#define BLDCFG_MEMORY_POWER_DOWN TRUE
132#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
133#define BLDCFG_ONLINE_SPARE FALSE
134#define BLDCFG_BANK_SWIZZLE TRUE
135#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
136#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
137#define BLDCFG_DQS_TRAINING_CONTROL TRUE
138#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
139#define BLDCFG_USE_BURST_MODE FALSE
140#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
141#define BLDCFG_ENABLE_ECC_FEATURE TRUE
142#define BLDCFG_ECC_REDIRECTION FALSE
143#define BLDCFG_SCRUB_DRAM_RATE 0
144#define BLDCFG_SCRUB_L2_RATE 0
145#define BLDCFG_SCRUB_L3_RATE 0
146#define BLDCFG_SCRUB_IC_RATE 0
147#define BLDCFG_SCRUB_DC_RATE 0
148#define BLDCFG_ECC_SYNC_FLOOD TRUE
149#define BLDCFG_ECC_SYMBOL_SIZE 4
150#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
151#define BLDCFG_1GB_ALIGN FALSE
152#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
Dave Frodin83405a12014-06-05 11:49:04 -0600[diff] [blame]153#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]154#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
155#define BLDCFG_IOMMU_SUPPORT FALSE
156#define OPTION_GFX_INIT_SVIEW FALSE
157//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
158
159//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
160#define BLDCFG_CFG_ABM_SUPPORT TRUE
161
162#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
163//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
164//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
165//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
166
167#ifdef PCIEX_BASE_ADDRESS
168#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
169#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
170#endif
171
172#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
173#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
174#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
175
176/* Process the options...
177 * This file include MUST occur AFTER the user option selection settings
178 */
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]179/*
180 * Customized OEM build configurations for FCH component
181 */
182// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
183// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
184// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
185// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
186// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
187// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
188// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
189// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
190// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
191// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
192// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
193// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
194// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
195// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
196// #define BLDCFG_AZALIA_SSID 0x780D1022
197// #define BLDCFG_SMBUS_SSID 0x780B1022
198// #define BLDCFG_IDE_SSID 0x780C1022
199// #define BLDCFG_SATA_AHCI_SSID 0x78011022
200// #define BLDCFG_SATA_IDE_SSID 0x78001022
201// #define BLDCFG_SATA_RAID5_SSID 0x78031022
202// #define BLDCFG_SATA_RAID_SSID 0x78021022
203// #define BLDCFG_EHCI_SSID 0x78081022
204// #define BLDCFG_OHCI_SSID 0x78071022
205// #define BLDCFG_LPC_SSID 0x780E1022
206// #define BLDCFG_SD_SSID 0x78061022
207// #define BLDCFG_XHCI_SSID 0x78121022
208// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
209// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
210// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
211// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
212// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
213// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
214// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
215// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
216// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
217// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
218// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
219
220CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
221{
222 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
223 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
224 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
225 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
226 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
227 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
228 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
229 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
230 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
231 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
232 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
233 { CPU_LIST_TERMINAL }
234};
235
236#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
237
238
239/* Include the files that instantiate the configuration definitions. */
240#include "cpuRegisters.h"
241#include "cpuFamRegisters.h"
242#include "cpuFamilyTranslation.h"
243#include "AdvancedApi.h"
244#include "heapManager.h"
245#include "CreateStruct.h"
246#include "cpuFeatures.h"
247#include "Table.h"
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]248#include "cpuEarlyInit.h"
249#include "cpuLateInit.h"
250#include "GnbInterface.h"
251
252 // This is the delivery package title, "BrazosPI"
253 // This string MUST be exactly 8 characters long
254#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
255
256 // This is the release version number of the AGESA component
257 // This string MUST be exactly 12 characters long
258#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
259
260/* MEMORY_BUS_SPEED */
261//#define DDR400_FREQUENCY 200 ///< DDR 400
262//#define DDR533_FREQUENCY 266 ///< DDR 533
263//#define DDR667_FREQUENCY 333 ///< DDR 667
264//#define DDR800_FREQUENCY 400 ///< DDR 800
265//#define DDR1066_FREQUENCY 533 ///< DDR 1066
266//#define DDR1333_FREQUENCY 667 ///< DDR 1333
267//#define DDR1600_FREQUENCY 800 ///< DDR 1600
268//#define DDR1866_FREQUENCY 933 ///< DDR 1866
269//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
270//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
271//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
272//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
273//
274///* QUANDRANK_TYPE*/
275//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
276//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
277//
278///* USER_MEMORY_TIMING_MODE */
279//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
280//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
281//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
282//
283///* POWER_DOWN_MODE */
284//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
285//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
286
287/*
288 * Agesa optional capabilities selection.
289 * Uncomment and mark FALSE those features you wish to include in the build.
290 * Comment out or mark TRUE those features you want to REMOVE from the build.
291 */
292
293#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
294#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
295#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
296#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
297#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
298#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
299#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
300#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
301#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
302#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
303#define DFLT_HPET_BASE_ADDRESS 0xFED00000
304#define DFLT_SMI_CMD_PORT 0xB0
305#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
306#define DFLT_GEC_BASE_ADDRESS 0xFED61000
307#define DFLT_AZALIA_SSID 0x780D1022
308#define DFLT_SMBUS_SSID 0x780B1022
309#define DFLT_IDE_SSID 0x780C1022
310#define DFLT_SATA_AHCI_SSID 0x78011022
311#define DFLT_SATA_IDE_SSID 0x78001022
312#define DFLT_SATA_RAID5_SSID 0x78031022
313#define DFLT_SATA_RAID_SSID 0x78021022
314#define DFLT_EHCI_SSID 0x78081022
315#define DFLT_OHCI_SSID 0x78071022
316#define DFLT_LPC_SSID 0x780E1022
317#define DFLT_SD_SSID 0x78061022
318#define DFLT_XHCI_SSID 0x78121022
319#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
320#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
321#define DFLT_FCH_GPP_LINK_CONFIG PortA4
322#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
323#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
324#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
325#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
326#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
327#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
328#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
329#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
330//#define BLDCFG_IR_PIN_CONTROL 0x33
331
Dave Frodin83405a12014-06-05 11:49:04 -0600[diff] [blame]332GPIO_CONTROL hp_abm_gpio[] = {
333 { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED
334 { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID
335 { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH
336 { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT
337 { 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L
338 { 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC
339 { 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L
340 { 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT
341 { 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT
342 { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]343 {-1}
344};
Dave Frodin83405a12014-06-05 11:49:04 -0600[diff] [blame]345#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0])
Kyösti Mälkkie75deb62014-06-26 09:12:54 +0300[diff] [blame]346
347// The following definitions specify the default values for various parameters in which there are
348// no clearly defined defaults to be used in the common file. The values below are based on product
349// and BKDG content, please consult the AGESA Memory team for consultation.
350#define DFLT_SCRUB_DRAM_RATE (0)
351#define DFLT_SCRUB_L2_RATE (0)
352#define DFLT_SCRUB_L3_RATE (0)
353#define DFLT_SCRUB_IC_RATE (0)
354#define DFLT_SCRUB_DC_RATE (0)
355#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
356#define DFLT_VRM_SLEW_RATE (5000)
357
358#include "PlatformInstall.h"