blob: 5d7bf86c5f204444db8b76ded4aea541f3825c99 [file] [log] [blame]
Patrick Georgi4d6ad832015-06-22 19:43:18 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright 2015 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Patrick Georgi4d6ad832015-06-22 19:43:18 +020015
16chip soc/nvidia/tegra210
Patrick Georgi4d6ad832015-06-22 19:43:18 +020017 device cpu_cluster 0 on
Patrick Georgi4d6ad832015-06-22 19:43:18 +020018 end
19
20 register "display_controller" = "TEGRA_ARM_DISPLAYA"
21 register "xres" = "2560"
22 register "yres" = "1800"
23
24 # bits per pixel and color depth
25 register "framebuffer_bits_per_pixel" = "32"
26 register "color_depth" = "12"
27
28 # framebuffer resolution
29 register "display_xres" = "1280"
30 register "display_yres" = "800"
31
32 register "href_to_sync" = "1"
33 register "hfront_porch" = "80"
34 register "hsync_width" = "80"
35 register "hback_porch" = "80"
36
37 register "vref_to_sync" = "1"
38 register "vfront_porch" = "4"
39 register "vsync_width" = "4"
40 register "vback_porch" = "4"
41 register "refresh" = "60"
42
43 # use value from kernel driver
44 register "pixel_clock" = "304416000"
45 register "win_opt" = "DSI_ENABLE"
46end