Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 14 | */ |
Ronald G. Minnich | a95a13b | 2013-03-05 17:07:40 -0800 | [diff] [blame] | 15 | |
Ronald G. Minnich | 665e3d2 | 2013-02-27 09:54:47 -0800 | [diff] [blame] | 16 | #include <stdint.h> |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 17 | #include <stdlib.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 18 | #include "i915io.h" |
| 19 | |
| 20 | struct iodef iodefs[] = { |
Ronald G. Minnich | b3b72f3 | 2013-03-13 14:35:01 -0700 | [diff] [blame] | 21 | {V, 0}, |
| 22 | {W, 1, "", PCH_GMBUS0, 0x00000000, 0}, |
| 23 | {R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0}, |
| 24 | {R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0}, |
| 25 | {W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0}, |
| 26 | {W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0}, |
| 27 | {M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0}, |
| 28 | {M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0}, |
| 29 | {R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10}, |
| 30 | {W, 1, "", FORCEWAKE_MT, 0x00010001, 0}, |
| 31 | {R, 1, "", FORCEWAKE_MT, 0x00010001, 0}, |
| 32 | {R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0}, |
| 33 | {R, 1, "", 0x13805c, 0x40000000, 0}, |
| 34 | {R, 1, "", 0xa180, 0x84100020, 0}, |
| 35 | {W, 1, "", FORCEWAKE_MT, 0x00010000, 0}, |
| 36 | {R, 1, "", 0x120000, 0x00000000, 0}, |
| 37 | {M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0}, |
| 38 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 39 | {M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0}, |
| 40 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, |
| 41 | {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, |
| 42 | {R, 1, "", _PIPEBCONF, 0x00000000, 0}, |
| 43 | {W, 1, "", _PIPEBCONF, 0x00000000, 0}, |
| 44 | {R, 1, "", 0x72008, 0x00000000, 0}, |
| 45 | {W, 1, "", 0x72008, 0x00000000, 0}, |
| 46 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, |
| 47 | {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, |
| 48 | {R, 1, "", _PIPEBCONF, 0x00000000, 0}, |
| 49 | {W, 1, "", _PIPEBCONF, 0x00000000, 0}, |
| 50 | {R, 1, "", 0x72008, 0x00000000, 0}, |
| 51 | {W, 1, "", 0x72008, 0x00000000, 0}, |
| 52 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, |
| 53 | {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, |
| 54 | {R, 1, "", _PIPEBCONF, 0x00000000, 0}, |
| 55 | {W, 1, "", _PIPEBCONF, 0x00000000, 0}, |
| 56 | {R, 1, "", 0x72008, 0x00000000, 0}, |
| 57 | {W, 1, "", 0x72008, 0x00000000, 300}, |
| 58 | {W, 1, "", CPU_VGACNTRL, 0x80000000, 0}, |
| 59 | {R, 1, "", CPU_VGACNTRL, 0x80000000, 0}, |
| 60 | {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, |
| 61 | {R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0}, |
| 62 | {R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0}, |
| 63 | {R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0}, |
| 64 | {M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0}, |
| 65 | {M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0}, |
| 66 | {M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0}, |
| 67 | {M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0}, |
| 68 | {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, |
| 69 | {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, |
| 70 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 71 | {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, |
| 72 | {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0}, |
| 73 | {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 74 | {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, |
| 75 | {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 76 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 77 | {M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, |
| 78 | {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 79 | {M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0}, |
| 80 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 81 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 82 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 83 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 84 | {M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0}, |
| 85 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 86 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 87 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 88 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 89 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 90 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 91 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 92 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 93 | {I,}, |
| 94 | {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0}, |
| 95 | {R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0}, |
| 96 | {M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0}, |
| 97 | {M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0}, |
| 98 | {M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0}, |
| 99 | {M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0}, |
| 100 | {R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0}, |
| 101 | {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0}, |
| 102 | {W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0}, |
| 103 | {R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200}, |
| 104 | {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0}, |
| 105 | {W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0}, |
| 106 | {R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200}, |
Vladimir Serbinenko | 9772f8d | 2014-08-31 22:12:24 +0200 | [diff] [blame] | 107 | {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, |
Ronald G. Minnich | b3b72f3 | 2013-03-13 14:35:01 -0700 | [diff] [blame] | 108 | {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 109 | {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 110 | {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 111 | {W, 1, "", 0x9404, 0x00002000, 0}, |
Vladimir Serbinenko | 9772f8d | 2014-08-31 22:12:24 +0200 | [diff] [blame] | 112 | {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, |
Ronald G. Minnich | b3b72f3 | 2013-03-13 14:35:01 -0700 | [diff] [blame] | 113 | {W, 1, "", IVB_CHICKEN3, 0x00000024, 0}, |
| 114 | {W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0}, |
| 115 | {W, 1, "", 0xb01c, 0x3c4fff8c, 0}, |
| 116 | {W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0}, |
| 117 | {R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0}, |
| 118 | {W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0}, |
| 119 | {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0}, |
| 120 | {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, |
| 121 | {R, 1, "", _DSPAADDR, 0x00000000, 0}, |
| 122 | {W, 1, "", _DSPAADDR, 0x00000000, 0}, |
| 123 | {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, |
| 124 | {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, |
| 125 | {R, 1, "", _DSPBCNTR, 0x00000000, 0}, |
| 126 | {W, 1, "", _DSPBCNTR, 0x00004000, 0}, |
| 127 | {R, 1, "", _DSPBADDR, 0x00000000, 0}, |
| 128 | {W, 1, "", _DSPBADDR, 0x00000000, 0}, |
| 129 | {R, 1, "", _DSPBSURF, 0x00000000, 0}, |
| 130 | {W, 1, "", _DSPBSURF, 0x00000000, 0}, |
| 131 | {R, 1, "", _DVSACNTR, 0x00000000, 0}, |
| 132 | {W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0}, |
| 133 | {R, 1, "", _DVSALINOFF, 0x00000000, 0}, |
| 134 | {W, 1, "", _DVSALINOFF, 0x00000000, 0}, |
| 135 | {R, 1, "", _DVSASURF, 0x00000000, 0}, |
| 136 | {W, 1, "", _DVSASURF, 0x00000000, 0}, |
| 137 | {W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0}, |
| 138 | {R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0}, |
| 139 | {W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0}, |
| 140 | {W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0}, |
Vladimir Serbinenko | 9772f8d | 2014-08-31 22:12:24 +0200 | [diff] [blame] | 141 | {W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0}, |
Ronald G. Minnich | b3b72f3 | 2013-03-13 14:35:01 -0700 | [diff] [blame] | 142 | {M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0}, |
| 143 | {M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0}, |
| 144 | {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0}, |
| 145 | {M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0}, |
| 146 | {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, |
| 147 | {M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0}, |
| 148 | {M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0}, |
| 149 | {M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0}, |
| 150 | {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, |
| 151 | {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, |
| 152 | {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, |
| 153 | {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, |
| 154 | {M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0}, |
| 155 | {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, |
| 156 | {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, |
| 157 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 158 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 159 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 160 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 161 | {I,}, |
| 162 | {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, |
| 163 | {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, |
| 164 | {R, 2, "", PCH_DP_D, 0x00000004, 0}, |
| 165 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, |
| 166 | {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, |
| 167 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, |
| 168 | {M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0}, |
| 169 | {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0}, |
| 170 | {W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0}, |
| 171 | {W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0}, |
| 172 | {W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0}, |
| 173 | {W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0}, |
| 174 | {W, 1, "", _PCH_FPA1, 0x00020e08, 0}, |
| 175 | {W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0}, |
| 176 | {W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0}, |
| 177 | {W, 1, "", _HBLANK_A, 0x0a9f09ff, 0}, |
| 178 | {W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0}, |
| 179 | {W, 1, "", _VTOTAL_A, 0x06d406a3, 0}, |
| 180 | {W, 1, "", _VBLANK_A, 0x06d406a3, 0}, |
| 181 | {W, 1, "", _VSYNC_A, 0x06b006a6, 0}, |
| 182 | {W, 1, "", _PIPEASRC, 0x09ff06a3, 0}, |
| 183 | {W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0}, |
| 184 | {W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0}, |
| 185 | {W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0}, |
| 186 | {W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0}, |
| 187 | {M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0}, |
| 188 | {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, |
| 189 | {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, |
| 190 | {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500}, |
| 191 | {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, |
| 192 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, |
| 193 | {R, 1, "", _PIPEASTAT, 0x00000000, 0}, |
| 194 | {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, |
| 195 | {R, 4562, "", _PIPEASTAT, 0x00000000, 0}, |
| 196 | {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, |
| 197 | {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, |
| 198 | {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, |
Vladimir Serbinenko | 9772f8d | 2014-08-31 22:12:24 +0200 | [diff] [blame] | 199 | {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, |
Ronald G. Minnich | b3b72f3 | 2013-03-13 14:35:01 -0700 | [diff] [blame] | 200 | {M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0}, |
| 201 | {W, 1, "", _DSPASTRIDE, 0x00002800, 0}, |
| 202 | {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, |
| 203 | {W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0}, |
| 204 | {W, 1, "", _DSPAADDR, 0x00000000, 0}, |
Vladimir Serbinenko | 9772f8d | 2014-08-31 22:12:24 +0200 | [diff] [blame] | 205 | {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, |
Ronald G. Minnich | b3b72f3 | 2013-03-13 14:35:01 -0700 | [diff] [blame] | 206 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 207 | {R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0}, |
| 208 | {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, |
| 209 | {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, |
| 210 | {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 211 | {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 212 | {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 213 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 214 | {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, |
| 215 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 216 | {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, |
| 217 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 218 | {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, |
| 219 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 220 | {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, |
| 221 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 222 | {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, |
| 223 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 224 | {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, |
| 225 | {M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0}, |
| 226 | {M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0}, |
| 227 | {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, |
| 228 | {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, |
| 229 | {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200}, |
| 230 | {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, |
| 231 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 232 | {R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, |
| 233 | {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, |
| 234 | {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, |
| 235 | {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 236 | {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 237 | {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, |
| 238 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 239 | {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, |
| 240 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 241 | {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, |
| 242 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 243 | {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, |
| 244 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 245 | {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, |
| 246 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 247 | {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, |
| 248 | {R, 1, "", 0x145d10, 0x2010040c, 0}, |
| 249 | {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, |
| 250 | {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, |
| 251 | {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, |
| 252 | {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, |
| 253 | {R, 1, "", _FDI_RXA_CTL, 0x00000040, 0}, |
| 254 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, |
| 255 | {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, |
| 256 | {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, |
| 257 | {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, |
| 258 | {W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0}, |
| 259 | {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, |
| 260 | {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, |
| 261 | {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, |
| 262 | {R, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, |
| 263 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, |
| 264 | {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, |
| 265 | {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, |
| 266 | {P, 1, "Set Palette"}, |
| 267 | {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, |
| 268 | {W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0}, |
| 269 | {R, 1, "", _PIPEASTAT, 0x00000000, 0}, |
| 270 | {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, |
| 271 | {R, 4533, "", _PIPEASTAT, 0x00000000, 0}, |
| 272 | {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, |
| 273 | {R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0}, |
Vladimir Serbinenko | 9772f8d | 2014-08-31 22:12:24 +0200 | [diff] [blame] | 274 | {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, |
| 275 | {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, |
Ronald G. Minnich | b3b72f3 | 2013-03-13 14:35:01 -0700 | [diff] [blame] | 276 | {R, 1, "", _DSPAADDR, 0x00000000, 0}, |
| 277 | {W, 1, "", _DSPAADDR, 0x00000000, 0}, |
| 278 | {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, |
| 279 | {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, |
| 280 | {R, 1, "", _PIPEASTAT, 0x00000000, 0}, |
| 281 | {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, |
| 282 | {R, 4392, "", _PIPEASTAT, 0x00000000, 0}, |
| 283 | {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, |
| 284 | {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, |
| 285 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 286 | {M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0}, |
| 287 | {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 288 | {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, |
| 289 | {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, |
| 290 | {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, |
| 291 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, |
| 292 | {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, |
| 293 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, |
| 294 | {M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0}, |
| 295 | {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0}, |
| 296 | {R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0}, |
| 297 | {R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0}, |
| 298 | {R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0}, |
| 299 | {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, |
| 300 | {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, |
| 301 | {R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, |
| 302 | {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, |
| 303 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, |
| 304 | {M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0}, |
| 305 | {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, |
| 306 | {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, |
| 307 | {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, |
| 308 | {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, |
| 309 | {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0}, |
| 310 | {M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0}, |
| 311 | {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0}, |
| 312 | {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100}, |
| 313 | {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, |
| 314 | {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, |
| 315 | {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, |
| 316 | {R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, |
| 317 | {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, |
| 318 | {I,}, |
| 319 | {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, |
| 320 | {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, |
| 321 | {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, |
| 322 | {I,}, |
| 323 | {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, |
| 324 | {I,}, |
| 325 | {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, |
| 326 | {I,}, |
| 327 | {M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0}, |
| 328 | {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, |
| 329 | {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, |
| 330 | {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, |
| 331 | {I,}, |
| 332 | {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, |
| 333 | {I,}, |
| 334 | {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, |
| 335 | {I,}, |
| 336 | {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, |
| 337 | {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, |
| 338 | {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, |
| 339 | {I,}, |
| 340 | {M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0}, |
| 341 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, |
| 342 | {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, |
| 343 | {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, |
| 344 | {R, 1, "", _PIPEADSL, 0x00000633, 500}, |
| 345 | {R, 1, "", _PIPEADSL, 0x00000652, 0}, |
| 346 | {R, 1, "", _PIPEASTAT, 0x00000000, 0}, |
| 347 | {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, |
| 348 | {R, 5085, "", _PIPEASTAT, 0x00000000, 0}, |
| 349 | {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, |
| 350 | {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, |
| 351 | {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, |
| 352 | {I,}, |
| 353 | }; |
Ronald G. Minnich | a95a13b | 2013-03-05 17:07:40 -0800 | [diff] [blame] | 354 | |
Paul Menzel | 4c960d4 | 2014-06-05 22:12:06 +0200 | [diff] [blame] | 355 | int niodefs = ARRAY_SIZE(iodefs); |