blob: 5600a6b63509576d612d11b815d54e43a76606dc [file] [log] [blame]
Damien Zammit126a2a82014-11-28 15:59:10 +11001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2008 coresystems GmbH
5## Copyright (C) 2014 Vladimir Serbinenko
6##
7## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Damien Zammit126a2a82014-11-28 15:59:10 +110016
17# -----------------------------------------------------------------
18entries
19
Damien Zammit126a2a82014-11-28 15:59:10 +110020# -----------------------------------------------------------------
21# Status Register A
Damien Zammit126a2a82014-11-28 15:59:10 +110022# -----------------------------------------------------------------
23# Status Register B
Damien Zammit126a2a82014-11-28 15:59:10 +110024# -----------------------------------------------------------------
25# Status Register C
26#96 4 r 0 status_c_rsvd
27#100 1 r 0 uf_flag
28#101 1 r 0 af_flag
29#102 1 r 0 pf_flag
30#103 1 r 0 irqf_flag
31# -----------------------------------------------------------------
32# Status Register D
33#104 7 r 0 status_d_rsvd
34#111 1 r 0 valid_cmos_ram
35# -----------------------------------------------------------------
36# Diagnostic Status Register
37#112 8 r 0 diag_rsvd1
38
39# -----------------------------------------------------------------
400 120 r 0 reserved_memory
41#120 264 r 0 unused
42
43# -----------------------------------------------------------------
44# RTC_BOOT_BYTE (coreboot hardcoded)
45384 1 e 4 boot_option
Nico Huberd23ee5d2016-08-11 22:45:55 +020046388 4 h 0 reboot_counter
Damien Zammit126a2a82014-11-28 15:59:10 +110047#390 2 r 0 unused?
48
49# -----------------------------------------------------------------
50# coreboot config options: console
51392 3 e 5 baud_rate
52395 4 e 6 debug_level
53#399 1 r 0 unused
54
55400 8 h 0 volume
56
57# coreboot config options: southbridge
58408 1 e 1 nmi
59409 2 e 7 power_on_after_fail
60
61#411 10 r 0 unused
62421 1 e 9 sata_mode
63#422 2 r 0 unused
64
65# coreboot config options: cpu
66424 1 e 2 hyper_threading
67#425 7 r 0 unused
68
69# coreboot config options: northbridge
70432 3 e 11 gfx_uma_size
71#435 549 r 0 unused
72
73# SandyBridge MRC Scrambler Seed values
74896 32 r 0 mrc_scrambler_seed
75928 32 r 0 mrc_scrambler_seed_s3
76960 16 r 0 mrc_scrambler_seed_chk
77
78# coreboot config options: check sums
79984 16 h 0 check_sum
80
81# -----------------------------------------------------------------
82
83enumerations
84
85#ID value text
861 0 Disable
871 1 Enable
882 0 Enable
892 1 Disable
904 0 Fallback
914 1 Normal
925 0 115200
935 1 57600
945 2 38400
955 3 19200
965 4 9600
975 5 4800
985 6 2400
995 7 1200
1006 1 Emergency
1016 2 Alert
1026 3 Critical
1036 4 Error
1046 5 Warning
1056 6 Notice
1066 7 Info
1076 8 Debug
1086 9 Spew
1097 0 Disable
1107 1 Enable
1117 2 Keep
1129 0 AHCI
1139 1 IDE
11411 0 32M
11511 1 64M
11611 2 96M
11711 3 128M
11811 4 160M
11911 5 192M
12011 6 224M
121
122# -----------------------------------------------------------------
123checksums
124
125checksum 392 415 984