Fabian Kunkel | cf05183 | 2016-07-27 17:42:39 +0200 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 5 | # Copyright (C) 2015 BAP - Bruhnspace Advanced Projects |
| 6 | # (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP) |
| 7 | # |
| 8 | # This program is free software; you can redistribute it and/or modify |
| 9 | # it under the terms of the GNU General Public License as published by |
| 10 | # the Free Software Foundation; version 2 of the License. |
| 11 | # |
| 12 | # This program is distributed in the hope that it will be useful, |
| 13 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | # GNU General Public License for more details. |
| 16 | |
| 17 | # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 18 | # BAP ODE E21XX has 2GB RAM soldered down on the Q7 |
Fabian Kunkel | cf05183 | 2016-07-27 17:42:39 +0200 | [diff] [blame] | 19 | # Memory setting for DDR-1333 |
| 20 | |
| 21 | # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage |
| 22 | # bits[3:0]: 1 = 128 SPD Bytes Used |
| 23 | # bits[6:4]: 1 = 256 SPD Bytes Total |
| 24 | # bit7 : 0 = CRC covers bytes 0 ~ 125 |
| 25 | 11 |
| 26 | |
| 27 | # 1 SPD Revision - |
| 28 | # 0x13 = Revision 1.3 |
| 29 | 13 |
| 30 | |
| 31 | # 2 Key Byte / DRAM Device Type |
| 32 | # bits[7:0]: 0x0b = DDR3 SDRAM |
| 33 | 0B |
| 34 | |
| 35 | # 3 Key Byte / Module Type |
| 36 | # bits[3:0]: 3 = SO-DIMM |
| 37 | # bits[7:4]: reserved |
| 38 | 03 |
| 39 | |
| 40 | # 4 SDRAM CHIP Density and Banks |
| 41 | # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip |
| 42 | # bits[6:4]: 0 = 3 (8 banks) |
| 43 | # bit7 : reserved |
| 44 | 04 |
| 45 | |
| 46 | # 5 SDRAM Addressing |
| 47 | # bits[2:0]: 1 = 10 Column Address Bits |
| 48 | # bits[5:3]: 3 = 15 Row Address Bits |
| 49 | # bits[7:6]: reserved |
| 50 | 19 |
| 51 | |
| 52 | # 6 Module Nominal Voltage, VDD |
| 53 | # bit0 : 0 = 1.5 V operable |
| 54 | # bit1 : 0 = NOT 1.35 V operable |
| 55 | # bit2 : 0 = NOT 1.25 V operable |
| 56 | # bits[7:3]: reserved |
| 57 | 00 |
| 58 | |
| 59 | # 7 Module Organization |
| 60 | # bits[2:0]: 2 = 16 bits |
| 61 | # bits[5:3]: 0 = 1 Rank |
| 62 | # bits[7:6]: reserved |
| 63 | 02 |
| 64 | |
| 65 | # 8 Module Memory Bus Width |
| 66 | # bits[2:0]: 3 = Primary bus width is 64 bits |
| 67 | # bits[4:3]: 1 = 1 bit (bus width extension ECC) |
| 68 | # bits[7:5]: reserved |
| 69 | 0B |
| 70 | |
| 71 | # 9 Fine Timebase (FTB) Dividend / Divisor |
| 72 | # bits[3:0]: 0x01 divisor |
| 73 | # bits[7:4]: 0x01 dividend |
| 74 | # 1/1 = 1ps |
| 75 | 11 |
| 76 | |
| 77 | # 10 Medium Timebase (MTB) Dividend |
| 78 | # 11 Medium Timebase (MTB) Divisor |
| 79 | # 1 / 8 = .125 ns - used for DDR3 |
| 80 | 01 08 |
| 81 | |
| 82 | # 12 SDRAM Minimum Cycle Time (tCKmin) |
| 83 | # 0x0C = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock) |
| 84 | 0C |
| 85 | |
| 86 | # 13 Reserved |
| 87 | 00 |
| 88 | |
| 89 | # 14 CAS Latencies Supported, Least Significant Byte |
| 90 | # 15 CAS Latencies Supported, Most Significant Byte |
| 91 | # Cas Latencies of 9 - 5 are supported (no 7) |
| 92 | 36 00 |
| 93 | |
| 94 | # 16 Minimum CAS Latency Time (tAAmin) |
| 95 | # 0x6C = 13.5ns - DDR3-1333H |
| 96 | 6C |
| 97 | |
| 98 | # 17 Minimum Write Recovery Time (tWRmin) |
| 99 | # 0x78 = tWR of 15ns - All DDR3 speed grades |
| 100 | 78 |
| 101 | |
| 102 | # 18 Minimum RAS# to CAS# Delay Time (tRCDmin) |
| 103 | # 0x6C = 13.5ns - DDR3-1333H |
| 104 | 6C |
| 105 | |
| 106 | # 19 Minimum Row Active to Row Active Delay Time (tRRDmin) |
| 107 | # 0x3C = 7.5ns |
| 108 | 3C |
| 109 | |
| 110 | # 20 Minimum Row Precharge Delay Time (tRPmin) |
| 111 | # 0x6C = 13.5ns - DDR3-1333H |
| 112 | 6C |
| 113 | |
| 114 | # 21 Upper Nibbles for tRAS and tRC |
| 115 | # bits[3:0]: tRAS most significant nibble = 1 (see byte 22) |
| 116 | # bits[7:4]: tRC most significant nibble = 1 (see byte 23) |
| 117 | 11 |
| 118 | |
| 119 | # 22 Minimum Active to Precharge Delay Time (tRASmin), LSB |
| 120 | # 0x120 = 36ns - DDR3-1333 (see byte 21) |
| 121 | 20 |
| 122 | |
| 123 | # 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB |
| 124 | # 0x18C = 49.5ns - DDR3-1333H (see byte 21) |
| 125 | 8C |
| 126 | |
| 127 | # 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB |
| 128 | # 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB |
| 129 | # 0x500 = 160ns - for 2 Gigabit chips |
| 130 | 80 07 |
| 131 | |
| 132 | # 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) |
| 133 | # 0x3c = 7.5 ns - All DDR3 SDRAM speed bins |
| 134 | 3C |
| 135 | |
| 136 | # 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) |
| 137 | # 0x3c = 7.5ns - All DDR3 SDRAM speed bins |
| 138 | 3C |
| 139 | |
| 140 | # 28 Upper Nibble for tFAWmin |
| 141 | # 29 Minimum Four Activate Window Delay Time (tFAWmin) |
| 142 | # 0x0168 = 45ns - DDR3-1333, 2 KB page size |
| 143 | 01 68 |
| 144 | |
| 145 | # 30 SDRAM Optional Feature |
| 146 | # bit0 : 1= RZQ/6 supported |
| 147 | # bit1 : 1 = RZQ/7 supported |
| 148 | # bits[6:2]: reserved |
| 149 | # bit7 : 0 = DLL Off mode supported |
| 150 | 03 |
| 151 | |
| 152 | # 31 SDRAM Thermal and Refresh Options |
| 153 | # bit0 : 0 = Temp up to 95c supported |
| 154 | # bit1 : 0 = 85-95c uses 2x refresh rate |
| 155 | # bit2 : 1 = Auto Self Refresh supported |
| 156 | # bit3 : 0 = no on die thermal sensor |
| 157 | # bits[6:4]: reserved |
| 158 | # bit7 : 0 = partial self refresh supported |
| 159 | 04 |
| 160 | |
| 161 | # 32 Module Thermal Sensor |
| 162 | # 0 = Thermal sensor not incorporated onto this assembly |
| 163 | 00 |
| 164 | |
| 165 | # 33 SDRAM Device Type |
| 166 | # bits[1:0]: 0 = Signal Loading not specified |
| 167 | # bits[3:2]: reserved |
| 168 | # bits[6:4]: 0 = Die count not specified |
| 169 | # bit7 : 0 = Standard Monolithic DRAM Device |
| 170 | 00 |
| 171 | |
| 172 | # 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) |
| 173 | # 35 Fine Offset for Minimum CAS Latency Time (tAAmin) |
| 174 | # 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) |
| 175 | # 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) |
| 176 | # 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) |
| 177 | 00 00 00 00 00 |
| 178 | |
| 179 | # 39 - 59 (reserved) |
| 180 | 00 00 00 00 00 00 00 00 |
| 181 | 00 00 00 00 00 00 00 00 |
| 182 | 00 00 00 00 00 |
| 183 | |
| 184 | # 60 Raw Card Extension, Module Nominal Height |
| 185 | # bits[4:0]: 0 = <= 15mm tall |
| 186 | # bits[7:5]: 0 = raw card revision 0-3 |
| 187 | 00 |
| 188 | |
| 189 | # 61 Module Maximum Thickness |
| 190 | # bits[3:0]: 0 = thickness front <= 1mm |
| 191 | # bits[7:4]: 0 = thinkness back <= 1mm |
| 192 | 00 |
| 193 | |
| 194 | # 62 Reference Raw Card Used |
| 195 | # bits[4:0]: 0 = Reference Raw card A used |
| 196 | # bits[6:5]: 0 = revision 0 |
| 197 | # bit7 : 0 = Reference raw cards A through AL |
| 198 | 00 |
| 199 | |
| 200 | # 63 Address Mapping from Edge Connector to DRAM |
| 201 | # bit0 : 0 = standard mapping (not mirrored) |
| 202 | # bits[7:1]: reserved |
| 203 | 00 |
| 204 | |
| 205 | # 64 - 116 (reserved) |
| 206 | 00 00 00 00 00 00 00 00 |
| 207 | 00 00 00 00 00 00 00 00 |
| 208 | 00 00 00 00 00 00 00 00 |
| 209 | 00 00 00 00 00 00 00 00 |
| 210 | 00 00 00 00 00 00 00 00 |
| 211 | 00 00 00 00 00 00 00 00 |
| 212 | 00 00 00 00 00 |
| 213 | |
| 214 | # 117 - 118 Module ID: Module Manufacturers JEDEC ID Code |
| 215 | # 0x80AD = Hynix |
| 216 | 80 AD |
| 217 | |
| 218 | # 119 Module ID: Module Manufacturing Location - oem specified |
| 219 | # 120 Module ID: Module Manufacture Year in BCD |
| 220 | # 0x00 = 2000 |
| 221 | 00 00 |
| 222 | |
| 223 | # 121 Module ID: Module Manufacture week |
| 224 | # 0x00 = 0th week |
| 225 | 00 |
| 226 | |
| 227 | # 122 - 125: Module Serial Number |
| 228 | 00 00 00 00 |
| 229 | |
| 230 | # 126 - 127: Cyclical Redundancy Code |
| 231 | 95 b9 |