Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 AMD |
| 5 | * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) |
| 6 | * Copyright (C) 2006 MSI |
| 7 | * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) |
| 8 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | unsigned int get_sbdn(unsigned bus); |
| 22 | |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 23 | #include <stdint.h> |
| 24 | #include <string.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <device/pnp_def.h> |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 28 | #include <cpu/x86/lapic.h> |
| 29 | #include <pc80/mc146818rtc.h> |
| 30 | #include <console/console.h> |
| 31 | #include <cpu/amd/model_fxx_rev.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 32 | #include <halt.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 33 | #include <northbridge/amd/amdk8/raminit.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 34 | #include <delay.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 35 | #include <cpu/x86/lapic.h> |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 36 | #include "northbridge/amd/amdk8/reset_test.c" |
| 37 | #include "northbridge/amd/amdk8/early_ht.c" |
Edward O'Callaghan | 9e308b9 | 2014-04-27 23:28:31 +1000 | [diff] [blame] | 38 | #include <superio/winbond/common/winbond.h> |
Edward O'Callaghan | 793a429 | 2014-04-03 14:30:58 +1100 | [diff] [blame] | 39 | #include <superio/winbond/w83627ehg/w83627ehg.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 40 | #include "southbridge/via/vt8237r/early_smbus.c" |
| 41 | #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 42 | #include <cpu/x86/bist.h> |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 43 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 44 | #include <spd.h> |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 45 | |
| 46 | #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) |
Uwe Hermann | 3a4ed15 | 2010-12-05 22:36:14 +0000 | [diff] [blame] | 47 | #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 48 | #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 49 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 50 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 51 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 52 | |
| 53 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 54 | { |
| 55 | return smbus_read_byte(device, address); |
| 56 | } |
| 57 | |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 58 | #include <reset.h> |
| 59 | void soft_reset(void) |
| 60 | { |
| 61 | uint8_t tmp; |
| 62 | |
| 63 | set_bios_reset(); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 64 | printk(BIOS_DEBUG, "soft reset\n"); |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 65 | |
| 66 | /* PCI reset */ |
| 67 | tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); |
| 68 | tmp |= 0x01; |
| 69 | pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); |
| 70 | |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 71 | halt(); |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 72 | } |
| 73 | |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 74 | #include "southbridge/via/k8t890/early_car.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 75 | #include <northbridge/amd/amdk8/amdk8.h> |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 76 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 77 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 78 | #include "northbridge/amd/amdk8/raminit.c" |
| 79 | #include "lib/generic_sdram.c" |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 80 | #include "cpu/amd/dualcore/dualcore.c" |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 81 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 82 | #include "cpu/amd/model_fxx/fidvid.c" |
| 83 | #include "northbridge/amd/amdk8/resourcemap.c" |
| 84 | |
| 85 | unsigned int get_sbdn(unsigned bus) |
| 86 | { |
Antonello Dettori | 837618b | 2016-09-03 10:47:40 +0200 | [diff] [blame] | 87 | pci_devfn_t dev; |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 88 | |
| 89 | dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, |
| 90 | PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); |
| 91 | return (dev >> 15) & 0x1f; |
| 92 | } |
| 93 | |
| 94 | static void sio_init(void) |
| 95 | { |
| 96 | u8 reg; |
| 97 | |
| 98 | pnp_enter_ext_func_mode(SERIAL_DEV); |
| 99 | /* We have 24MHz input. */ |
| 100 | reg = pnp_read_config(SERIAL_DEV, 0x24); |
| 101 | pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); |
| 102 | /* We have GPIO for KB/MS pin. */ |
| 103 | reg = pnp_read_config(SERIAL_DEV, 0x2a); |
| 104 | pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); |
| 105 | /* We have all RESTOUT and even some reserved bits, too. */ |
| 106 | reg = pnp_read_config(SERIAL_DEV, 0x2c); |
| 107 | pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); |
| 108 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 109 | |
| 110 | pnp_enter_ext_func_mode(ACPI_DEV); |
| 111 | pnp_set_logical_device(ACPI_DEV); |
| 112 | /* |
| 113 | * Set the delay rising time from PWROK_LP to PWROK_ST to |
| 114 | * 300 - 600ms, and 0 to vice versa. |
| 115 | */ |
| 116 | reg = pnp_read_config(ACPI_DEV, 0xe6); |
| 117 | pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); |
| 118 | /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ |
| 119 | reg = pnp_read_config(ACPI_DEV, 0xe4); |
| 120 | pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); |
| 121 | pnp_exit_ext_func_mode(ACPI_DEV); |
| 122 | |
| 123 | pnp_enter_ext_func_mode(GPIO_DEV); |
| 124 | pnp_set_logical_device(GPIO_DEV); |
| 125 | /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ |
| 126 | pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ |
| 127 | pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ |
| 128 | pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 129 | pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */ |
| 130 | pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 131 | pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ |
| 132 | pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ |
| 133 | pnp_exit_ext_func_mode(GPIO_DEV); |
| 134 | } |
| 135 | |
| 136 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 137 | { |
| 138 | static const uint16_t spd_addr[] = { |
| 139 | // Node 0 |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 140 | DIMM0, DIMM2, 0, 0, |
| 141 | DIMM1, DIMM3, 0, 0, |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 142 | // Node 1 |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 143 | DIMM4, DIMM6, 0, 0, |
| 144 | DIMM5, DIMM7, 0, 0, |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 145 | }; |
| 146 | unsigned bsp_apicid = 0; |
| 147 | int needs_reset = 0; |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 148 | struct sys_info *sysinfo = &sysinfo_car; |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 149 | |
| 150 | sio_init(); |
Edward O'Callaghan | 9e308b9 | 2014-04-27 23:28:31 +1000 | [diff] [blame] | 151 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 152 | console_init(); |
| 153 | enable_rom_decode(); |
| 154 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 155 | printk(BIOS_INFO, "now booting... romstage\n"); |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 156 | |
| 157 | /* Is this a CPU only reset? Or is this a secondary CPU? */ |
| 158 | if (!cpu_init_detectedx && boot_cpu()) { |
| 159 | /* Nothing special needs to be done to find bus 0. */ |
| 160 | /* Allow the HT devices to be found. */ |
| 161 | enumerate_ht_chain(); |
| 162 | } |
| 163 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 164 | printk(BIOS_INFO, "now booting... real_main\n"); |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 165 | |
| 166 | if (bist == 0) |
| 167 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 168 | |
| 169 | /* Halt if there was a built in self test failure. */ |
| 170 | report_bist_failure(bist); |
| 171 | |
| 172 | setup_default_resource_map(); |
| 173 | setup_coherent_ht_domain(); |
| 174 | wait_all_core0_started(); |
| 175 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 176 | printk(BIOS_INFO, "now booting... Core0 started\n"); |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 177 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 178 | #if CONFIG_LOGICAL_CPUS |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 179 | /* It is said that we should start core1 after all core0 launched. */ |
| 180 | start_other_cores(); |
| 181 | wait_all_other_cores_started(bsp_apicid); |
| 182 | #endif |
| 183 | init_timer(); |
| 184 | ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ |
| 185 | |
| 186 | needs_reset = optimize_link_coherent_ht(); |
| 187 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 188 | needs_reset |= k8t890_early_setup_ht(); |
| 189 | |
| 190 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 191 | printk(BIOS_DEBUG, "ht reset -\n"); |
Uwe Hermann | 2e9323e | 2010-11-14 21:48:14 +0000 | [diff] [blame] | 192 | soft_reset(); |
| 193 | } |
| 194 | |
| 195 | /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ |
| 196 | enable_fid_change(); |
| 197 | init_fidvid_bsp(bsp_apicid); |
| 198 | |
| 199 | /* Stop the APs so we can start them later in init. */ |
| 200 | allow_all_aps_stop(bsp_apicid); |
| 201 | |
| 202 | /* It's the time to set ctrl now. */ |
| 203 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 204 | |
| 205 | enable_smbus(); |
| 206 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 207 | post_cache_as_ram(); |
| 208 | } |