blob: 1f27f19c67956cd64b6b843cd837d55a6f268159 [file] [log] [blame]
Aaron Durbin27ce0942014-09-11 16:07:02 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Aaron Durbin27ce0942014-09-11 16:07:02 -050014 */
15
16#ifndef DRIVERS_GIC_H
17#define DRIVERS_GIC_H
18
19#include <stdint.h>
20
21#define NR(start, end) (((end) - (start)) / sizeof(uint32_t))
22
23struct gicd_mmio {
24 uint32_t ctlr; /* 0x000 - 0x003 */
25 uint32_t typer; /* 0x004 - 0x007 */
26 uint32_t iidr; /* 0x008 - 0x00b */
27 uint32_t reserved_1[NR(0xc, 0x80)]; /* 0x00c - 0x07f */
28 uint32_t igroupr[NR(0x80, 0x100)]; /* 0x080 - 0x0ff */
29 uint32_t isenabler[NR(0x100, 0x180)]; /* 0x100 - 0x17f */
30 uint32_t icenabler[NR(0x180, 0x200)]; /* 0x180 - 0x1ff */
31 uint32_t ispendr[NR(0x200, 0x280)]; /* 0x200 - 0x27f */
32 uint32_t icpendr[NR(0x280, 0x300)]; /* 0x280 - 0x2ff */
33 uint32_t isactiver[NR(0x300, 0x380)]; /* 0x300 - 0x37f */
34 uint32_t icactiver[NR(0x380, 0x400)]; /* 0x380 - 0x3ff */
35 uint32_t ipriorityr[NR(0x400, 0x7fc)]; /* 0x400 - 0x7fb */
36 uint32_t reserved_2[NR(0x7fc, 0x800)]; /* 0x7fc - 0x7ff */
37 uint32_t itargetsr[NR(0x800, 0xbfc)]; /* 0x800 - 0xbfb */
38 uint32_t reserved_3[NR(0xbfc, 0xc00)]; /* 0xbfc - 0x2ff */
39 uint32_t icfgr[NR(0xc00, 0xd00)]; /* 0xc00 - 0xcff */
40 uint32_t reserved_4[NR(0xd00, 0xe00)]; /* 0xd00 - 0xdff */
41 uint32_t nsacr[NR(0xe00, 0xf00)]; /* 0xe00 - 0xeff */
42 uint32_t sgir; /* 0xf00 - 0xf03 */
43 uint32_t reserved_5[NR(0xf04, 0xf10)]; /* 0xf04 - 0xf0f */
44 uint32_t cpendsgir[NR(0xf10, 0xf20)]; /* 0xf10 - 0xf1f */
45 uint32_t spendsgir[NR(0xf20, 0xf30)]; /* 0xf20 - 0xf2f */
46 uint32_t reserved_6[NR(0xf30, 0xfe8)]; /* 0xf30 - 0xfe7 */
47 uint32_t icpidr2; /* 0xfe8 - 0xfeb */
48 uint32_t reserved_7[NR(0xfec, 0x1000)]; /* 0xfec - 0xfff */
49};
50
51struct gicc_mmio {
52 uint32_t ctlr; /* 0x000 - 0x003 */
53 uint32_t pmr; /* 0x004 - 0x007 */
54 uint32_t bpr; /* 0x008 - 0x00b */
55 uint32_t iar; /* 0x00c - 0x00f */
56 uint32_t eoir; /* 0x010 - 0x013 */
57 uint32_t rpr; /* 0x014 - 0x017 */
58 uint32_t hppir; /* 0x018 - 0x01b */
59 uint32_t apbr; /* 0x01c - 0x01f */
60 uint32_t aiar; /* 0x020 - 0x023 */
61 uint32_t aeoir; /* 0x024 - 0x027 */
62 uint32_t ahppir; /* 0x028 - 0x02b */
63 uint32_t resered_1[NR(0x2c, 0xd0)]; /* 0x02c - 0x0cf */
64 uint32_t apr[NR(0xd0, 0xe0)]; /* 0x0d0 - 0x0df */
65 uint32_t nsapr[NR(0xe0, 0xf0)]; /* 0x0e0 - 0x0ef */
66 uint32_t resered_2[NR(0xf0, 0xfc)]; /* 0x0f0 - 0x0fb */
67 uint32_t iidr; /* 0x0fc - 0x0ff */
68 uint32_t reserved_3[NR(0x100, 0x1000)]; /* 0x100 - 0xfff */
69 uint32_t dir; /* 0x1000 - 0x1003 */
70};
71
72#undef NR
73
74#endif /* DRIVERS_GIC_H */