Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ICELAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Icelake support |
| 5 | |
| 6 | if SOC_INTEL_ICELAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 16 | select BOOT_DEVICE_SUPPORTS_WRITES |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 17 | select CACHE_MRC_SETTINGS |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 18 | select COMMON_FADT |
| 19 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Subrata Banik | ffb83be | 2019-04-29 13:58:43 +0530 | [diff] [blame] | 20 | select FSP_M_XIP |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 21 | select GENERIC_GPIO_LIB |
| 22 | select HAVE_FSP_GOP |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 23 | select HAVE_INTEL_FSP_REPO |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 24 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 25 | select HAVE_SMI_HANDLER |
| 26 | select IDT_IN_EVERY_STAGE |
| 27 | select INTEL_GMA_ACPI |
| 28 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 29 | select IOAPIC |
| 30 | select MRC_SETTINGS_PROTECT |
| 31 | select PARALLEL_MP |
| 32 | select PARALLEL_MP_AP_WORK |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 33 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | 55fb6b4 | 2018-12-19 16:50:57 +0530 | [diff] [blame] | 34 | select PLATFORM_USES_FSP2_1 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 35 | select REG_SCRIPT |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 36 | select SMP |
| 37 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
| 38 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Kyösti Mälkki | f5c0d61 | 2019-08-14 13:02:41 +0300 | [diff] [blame] | 39 | select CPU_INTEL_COMMON_SMM |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 40 | select SOC_INTEL_COMMON |
| 41 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 42 | select SOC_INTEL_COMMON_BLOCK |
| 43 | select SOC_INTEL_COMMON_BLOCK_ACPI |
| 44 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| 45 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 46 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 47 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 48 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 49 | select SOC_INTEL_COMMON_BLOCK_SA |
| 50 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 51 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 2fff391 | 2020-01-16 10:13:28 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_THERMAL |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_PCH_BASE |
| 54 | select SOC_INTEL_COMMON_RESET |
Arthur Heymans | b676837 | 2019-11-11 12:23:19 +0100 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 56 | select INTEL_CAR_NEM_ENHANCED |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 57 | select SSE2 |
| 58 | select SUPPORT_CPU_UCODE_IN_CBFS |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 59 | select TSC_MONOTONIC_TIMER |
| 60 | select UDELAY_TSC |
| 61 | select UDK_2017_BINDING |
| 62 | select DISPLAY_FSP_VERSION_INFO |
Subrata Banik | a0368a0 | 2019-06-04 14:16:02 +0530 | [diff] [blame] | 63 | select HECI_DISABLE_USING_SMM |
Subrata Banik | 9414600 | 2019-11-14 11:30:43 +0530 | [diff] [blame] | 64 | select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 65 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 66 | config DCACHE_RAM_BASE |
| 67 | default 0xfef00000 |
| 68 | |
| 69 | config DCACHE_RAM_SIZE |
| 70 | default 0x40000 |
| 71 | help |
| 72 | The size of the cache-as-ram region required during bootblock |
| 73 | and/or romstage. |
| 74 | |
| 75 | config DCACHE_BSP_STACK_SIZE |
| 76 | hex |
Subrata Banik | 645f244 | 2019-11-01 15:21:00 +0530 | [diff] [blame] | 77 | default 0x20400 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 78 | help |
| 79 | The amount of anticipated stack usage in CAR by bootblock and |
V Sowmya | 1dcc170 | 2019-10-14 14:42:34 +0530 | [diff] [blame] | 80 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 81 | sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 82 | |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 83 | config FSP_TEMP_RAM_SIZE |
| 84 | hex |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 85 | default 0x10000 |
| 86 | help |
| 87 | The amount of anticipated heap usage in CAR by FSP. |
| 88 | Refer to Platform FSP integration guide document to know |
| 89 | the exact FSP requirement for Heap setup. |
| 90 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 91 | config IFD_CHIPSET |
| 92 | string |
| 93 | default "icl" |
| 94 | |
| 95 | config IED_REGION_SIZE |
| 96 | hex |
| 97 | default 0x400000 |
| 98 | |
| 99 | config HEAP_SIZE |
| 100 | hex |
| 101 | default 0x8000 |
| 102 | |
| 103 | config MAX_ROOT_PORTS |
| 104 | int |
| 105 | default 16 |
| 106 | |
| 107 | config SMM_TSEG_SIZE |
| 108 | hex |
| 109 | default 0x800000 |
| 110 | |
| 111 | config SMM_RESERVED_SIZE |
| 112 | hex |
| 113 | default 0x200000 |
| 114 | |
| 115 | config PCR_BASE_ADDRESS |
| 116 | hex |
| 117 | default 0xfd000000 |
| 118 | help |
| 119 | This option allows you to select MMIO Base Address of sideband bus. |
| 120 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 121 | config MMCONF_BASE_ADDRESS |
| 122 | hex |
| 123 | default 0xc0000000 |
| 124 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 125 | config CPU_BCLK_MHZ |
| 126 | int |
| 127 | default 100 |
| 128 | |
| 129 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 130 | int |
| 131 | default 120 |
| 132 | |
| 133 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 134 | int |
| 135 | default 133 |
| 136 | |
| 137 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 138 | int |
| 139 | default 3 |
| 140 | |
| 141 | config SOC_INTEL_I2C_DEV_MAX |
| 142 | int |
| 143 | default 6 |
| 144 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 145 | config SOC_INTEL_UART_DEV_MAX |
| 146 | int |
| 147 | default 3 |
| 148 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 149 | config CONSOLE_UART_BASE_ADDRESS |
| 150 | hex |
| 151 | default 0xfe032000 |
| 152 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 153 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 154 | # Clock divider parameters for 115200 baud rate |
| 155 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 156 | hex |
| 157 | default 0x30 |
| 158 | |
| 159 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 160 | hex |
| 161 | default 0xc35 |
| 162 | |
| 163 | config CHROMEOS |
| 164 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 165 | |
| 166 | config VBOOT |
| 167 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 168 | select VBOOT_MUST_REQUEST_DISPLAY |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 169 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 170 | select VBOOT_VBNV_CMOS |
| 171 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 172 | |
| 173 | config C_ENV_BOOTBLOCK_SIZE |
| 174 | hex |
Subrata Banik | 458297c | 2019-01-07 14:24:27 +0530 | [diff] [blame] | 175 | default 0xC000 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 176 | |
| 177 | config CBFS_SIZE |
| 178 | hex |
| 179 | default 0x200000 |
| 180 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 181 | config FSP_HEADER_PATH |
Johanna Schander | f538d74 | 2019-12-08 11:04:09 +0100 | [diff] [blame] | 182 | default "3rdparty/fsp/IceLakeFspBinPkg/Include" |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 183 | |
| 184 | config FSP_FD_PATH |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 185 | default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" |
| 186 | |
Subrata Banik | 56626cf | 2020-02-27 19:39:22 +0530 | [diff] [blame] | 187 | config SOC_INTEL_ICELAKE_DEBUG_CONSENT |
| 188 | int "Debug Consent for ICL" |
| 189 | # USB DBC is more common for developers so make this default to 3 if |
| 190 | # SOC_INTEL_DEBUG_CONSENT=y |
| 191 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 192 | default 0 |
| 193 | help |
| 194 | This is to control debug interface on SOC. |
| 195 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 196 | PlatformDebugConsent in FspmUpd.h has the details. |
| 197 | |
| 198 | Desired platform debug types are |
| 199 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 200 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 201 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 202 | |
Subrata Banik | b14b55d | 2019-07-12 18:28:56 +0530 | [diff] [blame] | 203 | config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX |
| 204 | bool "Enable display over external PCIE GFX card" |
| 205 | select ALWAYS_LOAD_OPROM |
| 206 | help |
| 207 | It's possible to bring display through external graphics card over PCIE |
| 208 | in coreboot. This option enables graphics initialization with external |
| 209 | graphics card. |
| 210 | |
| 211 | Selected by mainboard that runs OpRom to perform display |
| 212 | initialization over attached PCIe GFX card. |
| 213 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 214 | endif |