soc/intel/icelake: Remove FSP-T option in Kconfig
This code lacks the temp_ram_init_params sybols so the FSP-T option
fails to build.
Change-Id: I2b6278bd64a3579ed3460af39ea244c7dfd51da4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 334dfbe..418c317 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -50,6 +50,8 @@
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select INTEL_CAR_NEM_ENHANCED
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
@@ -174,32 +176,6 @@
hex
default 0x200000
-choice
- prompt "Cache-as-ram implementation"
- default USE_ICELAKE_CAR_NEM_ENHANCED
- help
- This option allows you to select how cache-as-ram (CAR) is set up.
-
-config USE_ICELAKE_CAR_NEM_ENHANCED
- bool "Enhanced Non-evict mode"
- select SOC_INTEL_COMMON_BLOCK_CAR
- select INTEL_CAR_NEM_ENHANCED
- help
- A current limitation of NEM (Non-Evict mode) is that code and data
- sizes are derived from the requirement to not write out any modified
- cache line. With NEM, if there is no physical memory behind the
- cached area, the modified data will be lost and NEM results will be
- inconsistent. ENHANCED NEM guarantees that modified data is always
- kept in cache while clean data is replaced.
-
-config USE_ICELAKE_FSP_CAR
- bool "Use FSP CAR"
- select FSP_CAR
- help
- Use FSP APIs to initialize and tear down the Cache-As-Ram.
-
-endchoice
-
config FSP_HEADER_PATH
string "Location of FSP headers"
default "src/vendorcode/intel/fsp/fsp2_0/icelake/"