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review.coreboot.org / coreboot / 1dc8f0272bd222125d2d26cfa2b311f3d134f6ca / . / src / mainboard / siemens / mc_ehl / variants / mc_ehl5 / gpio.c
blob: a4ae8a5d2bd454cb1c278841d1eec8650e64c202 [file] [log] [blame]
Mario Scheithauerbdec0ea2023-02-27 12:44:26 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <baseboard/variants.h>
4#include <commonlib/helpers.h>
5
6/* Pad configuration in ramstage */
7static const struct pad_config gpio_table[] = {
8
9 /* Community 0 - GpioGroup GPP_B */
10 PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
11 PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
12 PAD_NC(GPP_B4, NONE), /* Not connected */
13 PAD_NC(GPP_B9, NONE), /* Not connected */
14 PAD_NC(GPP_B10, NONE), /* Not connected */
15 PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */
16 PAD_NC(GPP_B14, NONE), /* Not connected */
17 PAD_NC(GPP_B15, NONE), /* Not connected */
18 PAD_NC(GPP_B18, NONE), /* Not connected */
19 PAD_NC(GPP_B19, NONE), /* Not connected */
Mario Scheithauer7c90cb72023-11-09 09:56:26 +0100[diff] [blame]20 PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF2), /* PCHHOT_N */
Mario Scheithauerbdec0ea2023-02-27 12:44:26 +0100[diff] [blame]21
22 /* Community 0 - GpioGroup GPP_T */
23 PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), /* PSE_GBE0_INT */
24 PAD_CFG_GPO(GPP_T5, 1, DEEP), /* PSE_GBE0_RST_N */
25 PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
26 PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
27 PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */
28 PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */
29
30 /* Community 0 - GpioGroup GPP_G */
31 PAD_NC(GPP_G8, NONE), /* Not connected */
32 PAD_NC(GPP_G9, NONE), /* Not connected */
33 PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */
34
35 /* Community 1 - GpioGroup GPP_V */
36 PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */
37 PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), /* EMMC_DATA0 */
38 PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), /* EMMC_DATA1 */
39 PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), /* EMMC_DATA2 */
40 PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), /* EMMC_DATA3 */
41 PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), /* EMMC_DATA4 */
42 PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), /* EMMC_DATA5 */
43 PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), /* EMMC_DATA6 */
44 PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */
45 PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */
46 PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */
47 PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET */
48
49 /* Community 1 - GpioGroup GPP_H */
50 PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), /* PSE_GBE1_INT */
51 PAD_CFG_GPO(GPP_H1, 1, DEEP), /* PSE_GBE1_RST_N */
52 PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */
53 PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */
54 PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* PCIE_CLKREQ4_N */
55 PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* PCIE_CLKREQ5_N */
56
57 /* Community 1 - GpioGroup GPP_D */
58 PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCIE_CLKREQ0_N */
59 PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCIE_CLKREQ1_N */
60 PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* PCIE_CLKREQ2_N */
61 PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* PCIE_CLKREQ3_N */
62
63 /* Community 1 - GpioGroup GPP_U */
64 PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1), /* GBE_INT */
65 PAD_CFG_GPO(GPP_U1, 1, DEEP), /* GBE_RST_N */
66 PAD_NC(GPP_U12, NONE), /* Not connected */
67 PAD_NC(GPP_U13, NONE), /* Not connected */
68 PAD_NC(GPP_U16, NONE), /* Not connected */
69 PAD_NC(GPP_U17, NONE), /* Not connected */
70 PAD_NC(GPP_U18, NONE), /* Not connected */
71
72 /* Community 2 - GpioGroup DSW */
73 PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), /* ACPRESENT */
74 PAD_NC(GPD9, NONE), /* Not connected */
75 PAD_NC(GPD11, NONE), /* Not connected */
76
77 /* Community 3 - GpioGroup GPP_S */
78 PAD_NC(GPP_S0, NONE), /* Not connected */
79 PAD_NC(GPP_S1, NONE), /* Not connected */
80
81 /* Community 3 - GpioGroup GPP_A */
82 PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */
83 PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */
84 PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */
85 PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */
86 PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */
87 PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */
88 PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */
89 PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */
90 PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */
91 PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */
92 PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */
93 PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD3 */
94 PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD2 */
95 PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD1 */
96 PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD0 */
97 PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCLK */
98 PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCTL */
99 PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCLK */
100 PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCTL */
101 PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD3 */
102 PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD2 */
103 PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD1 */
104 PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD0 */
105 PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */
106
107 /* Community 4 - GpioGroup GPP_C */
108 PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */
109 PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */
110 PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE1_MDC */
111 PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE1_MDIO */
112 PAD_NC(GPP_C8, NONE), /* Not connected */
113 PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */
114 PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */
115 PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */
116 PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */
117
118 /* Community 4 - GpioGroup GPP_F */
119 PAD_NC(GPP_F1, NONE), /* Not connected */
120 PAD_NC(GPP_F3, NONE), /* Not connected */
121 PAD_NC(GPP_F8, NONE), /* Not connected */
122 PAD_NC(GPP_F11, NONE), /* Not connected */
123 PAD_NC(GPP_F12, NONE), /* Not connected */
124 PAD_NC(GPP_F13, NONE), /* Not connected */
125 PAD_NC(GPP_F14, NONE), /* Not connected */
126 PAD_NC(GPP_F15, NONE), /* Not connected */
127 PAD_NC(GPP_F16, NONE), /* Not connected */
128 PAD_NC(GPP_F17, NONE), /* Not connected */
129 PAD_CFG_GPO(GPP_F20, 0, DEEP), /* LED_BIOS_DONE */
130
131 /* Community 4 - GpioGroup GPP_E */
132 PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */
133 PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* M.2_SSD_SATA_DEVSLP_1 */
134 PAD_NC(GPP_E15, NONE), /* Not connected */
135 PAD_NC(GPP_E16, NONE), /* Not connected */
Mario Scheithauerbdec0ea2023-02-27 12:44:26 +0100[diff] [blame]136 PAD_NC(GPP_E23, NONE), /* Not connected */
137
138 /* Community 5 - GpioGroup GPP_R */
139 PAD_NC(GPP_R1, NONE), /* Not connected */
140 PAD_NC(GPP_R3, NONE), /* Not connected */
141};
142
143/* Early pad configuration in bootblock */
144static const struct pad_config early_gpio_table[] = {
145};
146
147const struct pad_config *variant_gpio_table(size_t *num)
148{
149 *num = ARRAY_SIZE(gpio_table);
150 return gpio_table;
151}
152
153const struct pad_config *variant_early_gpio_table(size_t *num)
154{
155 *num = ARRAY_SIZE(early_gpio_table);
156 return early_gpio_table;
157}