Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame^] | 23 | #define __PRE_RAM__ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 24 | |
| 25 | #include <delay.h> |
| 26 | |
| 27 | #include <stdint.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <arch/romcc_io.h> |
| 30 | #include <device/pci_def.h> |
| 31 | #include <device/pnp_def.h> |
| 32 | #include <cpu/x86/lapic.h> |
| 33 | |
| 34 | #include "option_table.h" |
| 35 | #include "pc80/mc146818rtc_early.c" |
| 36 | |
| 37 | #include "pc80/serial.c" |
| 38 | #include "arch/i386/lib/console.c" |
| 39 | #include <cpu/x86/bist.h> |
| 40 | |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 41 | #include "lib/ramtest.c" |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 42 | #include "southbridge/intel/i3100/i3100_early_smbus.c" |
| 43 | #include "southbridge/intel/i3100/i3100_early_lpc.c" |
| 44 | #include "reset.c" |
| 45 | #include "superio/intel/i3100/i3100_early_serial.c" |
| 46 | #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" |
| 47 | |
| 48 | /* Data */ |
| 49 | #define UART_RBR 0x00 |
| 50 | #define UART_TBR 0x00 |
| 51 | |
| 52 | /* Control */ |
| 53 | #define UART_IER 0x01 |
| 54 | #define UART_IIR 0x02 |
| 55 | #define UART_FCR 0x02 |
| 56 | #define UART_LCR 0x03 |
| 57 | #define UART_MCR 0x04 |
| 58 | #define UART_DLL 0x00 |
| 59 | #define UART_DLM 0x01 |
| 60 | |
| 61 | /* Status */ |
| 62 | #define UART_LSR 0x05 |
| 63 | #define UART_MSR 0x06 |
| 64 | #define UART_SCR 0x07 |
| 65 | |
| 66 | #define SIO_GPIO_BASE 0x680 |
| 67 | #define SIO_XBUS_BASE 0x4880 |
| 68 | |
| 69 | #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) |
| 70 | #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) |
| 71 | |
| 72 | #define IA32_PERF_STS 0x198 |
| 73 | #define IA32_PERF_CTL 0x199 |
| 74 | #define MSR_THERM2_CTL 0x19D |
| 75 | #define IA32_MISC_ENABLES 0x1A0 |
| 76 | |
| 77 | /* SATA */ |
| 78 | #define SATA_MAP 0x90 |
| 79 | |
| 80 | #define SATA_MODE_IDE 0x00 |
| 81 | #define SATA_MODE_AHCI 0x01 |
| 82 | |
| 83 | /* RCBA registers */ |
| 84 | #define RCBA 0xF0 |
| 85 | #define DEFAULT_RCBA 0xFEA00000 |
| 86 | |
| 87 | #define RCBA_RPC 0x0224 /* 32 bit */ |
| 88 | |
| 89 | #define RCBA_TCTL 0x3000 /* 8 bit */ |
| 90 | |
| 91 | #define RCBA_D31IP 0x3100 /* 32 bit */ |
| 92 | #define RCBA_D30IP 0x3104 /* 32 bit */ |
| 93 | #define RCBA_D29IP 0x3108 /* 32 bit */ |
| 94 | #define RCBA_D28IP 0x310C /* 32 bit */ |
| 95 | #define RCBA_D31IR 0x3140 /* 16 bit */ |
| 96 | #define RCBA_D30IR 0x3142 /* 16 bit */ |
| 97 | #define RCBA_D29IR 0x3144 /* 16 bit */ |
| 98 | #define RCBA_D28IR 0x3146 /* 16 bit */ |
| 99 | |
| 100 | #define RCBA_RTC 0x3400 /* 32 bit */ |
| 101 | #define RCBA_HPTC 0x3404 /* 32 bit */ |
| 102 | #define RCBA_GCS 0x3410 /* 32 bit */ |
| 103 | #define RCBA_BUC 0x3414 /* 8 bit */ |
| 104 | #define RCBA_FD 0x3418 /* 32 bit */ |
| 105 | #define RCBA_PRC 0x341C /* 32 bit */ |
| 106 | |
| 107 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 108 | { |
| 109 | /* nothing to do */ |
| 110 | } |
| 111 | static inline int spd_read_byte(u16 device, u8 address) |
| 112 | { |
| 113 | return smbus_read_byte(device, address); |
| 114 | } |
| 115 | |
| 116 | #include "northbridge/intel/i3100/raminit.h" |
| 117 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 118 | #include "northbridge/intel/i3100/memory_initialized.c" |
| 119 | #include "northbridge/intel/i3100/raminit.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 120 | #include "lib/generic_sdram.c" |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 121 | #include "northbridge/intel/i3100/reset_test.c" |
| 122 | #include "debug.c" |
| 123 | |
| 124 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
| 125 | #include "southbridge/intel/i3100/cmos_failover.c" |
| 126 | #endif |
| 127 | |
| 128 | void early_config(void) { |
| 129 | device_t dev; |
| 130 | u32 gcs, rpc, fd; |
| 131 | |
| 132 | /* Enable RCBA */ |
| 133 | pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); |
| 134 | |
| 135 | /* Disable watchdog */ |
| 136 | gcs = readl(DEFAULT_RCBA + RCBA_GCS); |
| 137 | gcs |= (1 << 5); /* No reset */ |
| 138 | writel(gcs, DEFAULT_RCBA + RCBA_GCS); |
| 139 | |
| 140 | /* Configure PCIe port B as 4x */ |
| 141 | rpc = readl(DEFAULT_RCBA + RCBA_RPC); |
| 142 | rpc |= (3 << 0); |
| 143 | writel(rpc, DEFAULT_RCBA + RCBA_RPC); |
| 144 | |
| 145 | /* Disable Modem, Audio, PCIe ports 2/3/4 */ |
| 146 | fd = readl(DEFAULT_RCBA + RCBA_FD); |
| 147 | fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); |
| 148 | writel(fd, DEFAULT_RCBA + RCBA_FD); |
| 149 | |
| 150 | /* Enable HPET */ |
| 151 | writel((1 << 7), DEFAULT_RCBA + RCBA_HPTC); |
| 152 | |
| 153 | /* Improve interrupt routing |
| 154 | * D31:F2 SATA INTB# -> PIRQD |
| 155 | * D31:F3 SMBUS INTB# -> PIRQD |
| 156 | * D31:F4 CHAP INTD# -> PIRQA |
| 157 | * D29:F0 USB1#1 INTA# -> PIRQH |
| 158 | * D29:F1 USB1#2 INTB# -> PIRQD |
| 159 | * D29:F7 USB2 INTA# -> PIRQH |
| 160 | * D28:F0 PCIe Port 1 INTA# -> PIRQE |
| 161 | */ |
| 162 | |
| 163 | writew(0x0230, DEFAULT_RCBA + RCBA_D31IR); |
| 164 | writew(0x3210, DEFAULT_RCBA + RCBA_D30IR); |
| 165 | writew(0x3237, DEFAULT_RCBA + RCBA_D29IR); |
| 166 | writew(0x3214, DEFAULT_RCBA + RCBA_D28IR); |
| 167 | |
| 168 | /* Setup sata mode */ |
| 169 | pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); |
| 170 | } |
| 171 | |
| 172 | void real_main(unsigned long bist) |
| 173 | { |
| 174 | /* int boot_mode = 0; */ |
| 175 | |
| 176 | static const struct mem_controller mch[] = { |
| 177 | { |
| 178 | .node_id = 0, |
| 179 | .f0 = PCI_DEV(0, 0x00, 0), |
| 180 | .f1 = PCI_DEV(0, 0x00, 1), |
| 181 | .f2 = PCI_DEV(0, 0x00, 2), |
| 182 | .f3 = PCI_DEV(0, 0x00, 3), |
| 183 | .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 }, |
| 184 | .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 }, |
| 185 | } |
| 186 | }; |
| 187 | |
| 188 | if (bist == 0) { |
| 189 | enable_lapic(); |
| 190 | } |
| 191 | |
| 192 | /* Setup the console */ |
| 193 | i3100_enable_superio(); |
| 194 | i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE); |
| 195 | uart_init(); |
| 196 | console_init(); |
| 197 | |
| 198 | /* Halt if there was a built in self test failure */ |
| 199 | report_bist_failure(bist); |
| 200 | |
| 201 | /* Perform early board specific init */ |
| 202 | early_config(); |
| 203 | |
| 204 | /* Prevent the TCO timer from rebooting us */ |
| 205 | i3100_halt_tco_timer(); |
| 206 | |
| 207 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 208 | enable_smbus(); |
| 209 | |
| 210 | /* Enable SpeedStep and automatic thermal throttling */ |
| 211 | { |
| 212 | msr_t msr; |
| 213 | u16 perf; |
| 214 | |
| 215 | msr = rdmsr(IA32_MISC_ENABLES); |
| 216 | msr.lo |= (1 << 3) | (1 << 16); |
| 217 | wrmsr(IA32_MISC_ENABLES, msr); |
| 218 | |
| 219 | /* Set CPU frequency/voltage to maximum */ |
| 220 | |
| 221 | /* Read performance status register and keep |
| 222 | * bits 47:32, where BUS_RATIO_MAX and VID_MAX |
| 223 | * are encoded |
| 224 | */ |
| 225 | msr = rdmsr(IA32_PERF_STS); |
| 226 | perf = msr.hi & 0x0000ffff; |
| 227 | |
| 228 | /* Write VID_MAX & BUS_RATIO_MAX to |
| 229 | * performance control register |
| 230 | */ |
| 231 | msr = rdmsr(IA32_PERF_CTL); |
| 232 | msr.lo &= 0xffff0000; |
| 233 | msr.lo |= perf; |
| 234 | wrmsr(IA32_PERF_CTL, msr); |
| 235 | } |
| 236 | |
| 237 | /* Initialize memory */ |
| 238 | sdram_initialize(ARRAY_SIZE(mch), mch); |
| 239 | } |
| 240 | |
Stefan Reinauer | fbb8a01 | 2009-10-26 16:48:27 +0000 | [diff] [blame] | 241 | /* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */ |
| 242 | #include "cpu/intel/model_6ex/cache_as_ram_disable.c" |