Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 2 | |
| 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 5 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 7 | #include <cbmem.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 8 | #include <cpu/intel/smm_reloc.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 9 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 10 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 11 | #include <program_loading.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 12 | #include "sandybridge.h" |
| 13 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 14 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 15 | { |
| 16 | /* Base of TSEG is top of usable DRAM */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 17 | return pci_read_config32(HOST_BRIDGE, TSEGMB); |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 18 | } |
| 19 | |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 20 | void *cbmem_top_chipset(void) |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 21 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 22 | return (void *)smm_region_start(); |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 23 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 24 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 25 | static uintptr_t northbridge_get_tseg_base(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 26 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 27 | return ALIGN_DOWN(smm_region_start(), 1 * MiB); |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 28 | } |
| 29 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 30 | static size_t northbridge_get_tseg_size(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 31 | { |
| 32 | return CONFIG_SMM_TSEG_SIZE; |
| 33 | } |
| 34 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 35 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 36 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 37 | *start = northbridge_get_tseg_base(); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 38 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 39 | } |
| 40 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 41 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 42 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 43 | uintptr_t top_of_ram = (uintptr_t)cbmem_top(); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 44 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 45 | /* |
| 46 | * Cache 8MiB below the top of ram. On sandybridge systems the top of |
Elyes HAOUAS | ef90609 | 2020-02-20 19:41:17 +0100 | [diff] [blame] | 47 | * RAM under 4GiB is the start of the TSEG region. It is required to |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 48 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 49 | * for ramstage before setting up the entire RAM as cacheable. |
| 50 | */ |
| 51 | postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 52 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 53 | /* |
| 54 | * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 55 | * is where the TSEG region resides. However, it is not restricted |
| 56 | * to SMM mode until SMM has been relocated. By setting the region |
| 57 | * to cacheable it provides faster access when relocating the SMM |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 58 | * handler as well as using the TSEG region for other purposes. |
| 59 | */ |
| 60 | postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 61 | } |