| Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| Tim Crawford | 3a5217a | 2022-07-26 14:04:04 -0600 | [diff] [blame] | 3 | #include <soc/ramstage.h> |
| Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 4 | |
| Tim Crawford | 3a5217a | 2022-07-26 14:04:04 -0600 | [diff] [blame] | 5 | void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 6 | { |
| Tim Crawford | 3a5217a | 2022-07-26 14:04:04 -0600 | [diff] [blame] | 7 | params->PchLegacyIoLowLatency = 1; |
| 8 | |
| Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 9 | // PEG0 Config |
| 10 | params->CpuPcieRpAdvancedErrorReporting[0] = 0; |
| 11 | params->CpuPcieRpLtrEnable[0] = 1; |
| 12 | params->CpuPcieRpPtmEnabled[0] = 0; |
| 13 | |
| 14 | // PEG2 Config |
| 15 | params->CpuPcieRpAdvancedErrorReporting[2] = 0; |
| 16 | params->CpuPcieRpLtrEnable[2] = 1; |
| 17 | params->CpuPcieRpPtmEnabled[2] = 0; |
| 18 | |
| 19 | // Remap PEG2 as PEG1 |
| 20 | params->CpuPcieRpFunctionSwap = 1; |
| Tim Crawford | 1d3e6eb | 2023-07-31 14:15:27 -0600 | [diff] [blame^] | 21 | |
| 22 | // Enable reporting CPU C10 state over eSPI |
| 23 | params->PchEspiHostC10ReportEnable = 1; |
| Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 24 | } |