Tim Crawford | fa5a475 | 2022-11-01 11:59:02 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <mainboard/gpio.h> |
| 4 | #include <soc/ramstage.h> |
Tim Crawford | fa5a475 | 2022-11-01 11:59:02 -0600 | [diff] [blame] | 5 | |
| 6 | void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 7 | { |
| 8 | params->CnviRfResetPinMux = 0x194CE404; // GPP_F4 |
| 9 | params->CnviClkreqPinMux = 0x394CE605; // GPP_F5 |
| 10 | |
| 11 | params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 |
| 12 | params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 |
| 13 | params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6 |
| 14 | params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7 |
| 15 | |
| 16 | params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12 |
| 17 | params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 |
| 18 | |
| 19 | params->SataPortsSolidStateDrive[1] = 1; |
Tim Crawford | 1d3e6eb | 2023-07-31 14:15:27 -0600 | [diff] [blame^] | 20 | |
| 21 | // Enable reporting CPU C10 state over eSPI |
| 22 | params->PchEspiHostC10ReportEnable = 1; |
Tim Crawford | fa5a475 | 2022-11-01 11:59:02 -0600 | [diff] [blame] | 23 | } |
| 24 | |
| 25 | static void mainboard_init(void *chip_info) |
| 26 | { |
| 27 | mainboard_configure_gpios(); |
| 28 | } |
| 29 | |
| 30 | struct chip_operations mainboard_ops = { |
| 31 | .init = mainboard_init, |
| 32 | }; |