Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 2 | |
| 3 | #include <commonlib/helpers.h> |
Arthur Heymans | 481c52d | 2019-11-08 17:05:04 +0100 | [diff] [blame] | 4 | #include <cpu/intel/msr.h> |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 5 | #include <cpu/x86/cache.h> |
| 6 | #include <cpu/x86/cr.h> |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 7 | #include <cpu/x86/msr.h> |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 8 | #include <cpu/x86/mtrr.h> |
| 9 | #include <cpu/x86/post_code.h> |
| 10 | #include <rules.h> |
| 11 | #include <intelblocks/msr.h> |
| 12 | |
Kyösti Mälkki | 7522a8f | 2020-11-20 16:47:38 +0200 | [diff] [blame] | 13 | .section .init, "ax", @progbits |
| 14 | |
Patrick Rudolph | 2b77112 | 2020-11-30 13:52:42 +0100 | [diff] [blame] | 15 | .code32 |
Arthur Heymans | 64c9c6d | 2019-11-25 09:45:40 +0100 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * macro: find_free_mtrr |
| 19 | * Clobbers: %eax, %ebx, %ecx, %edx. |
| 20 | * Returns: |
| 21 | * %ebx contains the number of freely available MTRR's. |
| 22 | * It should be checked against 0. |
| 23 | * %ecx holds the MTRR_BASE of the free MTRR. |
| 24 | */ |
| 25 | .macro find_free_mtrr |
| 26 | /* Figure out how many MTRRs we have */ |
| 27 | mov $MTRR_CAP_MSR, %ecx |
| 28 | rdmsr |
| 29 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 30 | |
| 31 | /* Find a free variable MTRR */ |
| 32 | movl $MTRR_PHYS_MASK(0), %ecx |
| 33 | 1: |
| 34 | rdmsr |
| 35 | test $MTRR_PHYS_MASK_VALID, %eax |
| 36 | jz 2f |
| 37 | addl $2, %ecx |
| 38 | dec %ebx |
| 39 | jnz 1b |
| 40 | 2: |
| 41 | /* %ecx needs to hold the MTRR_BASE */ |
| 42 | decl %ecx |
| 43 | .endm |
| 44 | |
Arthur Heymans | 99a48bc | 2019-11-25 09:56:20 +0100 | [diff] [blame] | 45 | /* |
| 46 | * macro: clear_car |
| 47 | * Clears the region between CONFIG_DCACHE_RAM_BASE and |
| 48 | * CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE to populate |
| 49 | * cachelines. |
| 50 | * Clobbers %eax, %ecx, %edi. |
| 51 | */ |
| 52 | .macro clear_car |
| 53 | /* Clear the cache memory region. This will also fill up the cache */ |
| 54 | movl $CONFIG_DCACHE_RAM_BASE, %edi |
| 55 | movl $CONFIG_DCACHE_RAM_SIZE, %ecx |
| 56 | shr $0x02, %ecx |
| 57 | xor %eax, %eax |
| 58 | cld |
| 59 | rep stosl |
| 60 | .endm |
| 61 | |
Arthur Heymans | cd96fed5 | 2021-06-23 10:48:28 +0200 | [diff] [blame] | 62 | /* |
| 63 | * macro: is_bootguard_nem |
| 64 | * Checks if the Bootguard ACM has enabled non eviction mode |
| 65 | * Clobbers %eax, %ecx, %edx |
| 66 | * Returns %eax and sets/unsets zero flag |
| 67 | */ |
| 68 | .macro is_bootguard_nem |
Arthur Heymans | 6da7fa2 | 2021-06-23 10:52:01 +0200 | [diff] [blame] | 69 | #if CONFIG(SOC_INTEL_NO_BOOTGUARD_MSR) |
| 70 | xorl %eax, %eax |
| 71 | #else |
Arthur Heymans | cd96fed5 | 2021-06-23 10:48:28 +0200 | [diff] [blame] | 72 | movl $MSR_BOOT_GUARD_SACM_INFO, %ecx |
| 73 | rdmsr |
| 74 | andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax |
Arthur Heymans | 6da7fa2 | 2021-06-23 10:52:01 +0200 | [diff] [blame] | 75 | #endif |
Arthur Heymans | cd96fed5 | 2021-06-23 10:48:28 +0200 | [diff] [blame] | 76 | .endm |
| 77 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 78 | .global bootblock_pre_c_entry |
| 79 | bootblock_pre_c_entry: |
| 80 | |
| 81 | post_code(0x20) |
| 82 | |
Arthur Heymans | 481c52d | 2019-11-08 17:05:04 +0100 | [diff] [blame] | 83 | /* Bootguard sets up its own CAR and needs separate handling */ |
| 84 | check_boot_guard: |
Arthur Heymans | cd96fed5 | 2021-06-23 10:48:28 +0200 | [diff] [blame] | 85 | is_bootguard_nem |
Arthur Heymans | 481c52d | 2019-11-08 17:05:04 +0100 | [diff] [blame] | 86 | jz no_bootguard |
| 87 | |
| 88 | /* Disable PBE timer */ |
| 89 | movl $MSR_BC_PBEC, %ecx |
| 90 | movl $B_STOP_PBET, %eax |
| 91 | xorl %edx, %edx |
| 92 | wrmsr |
| 93 | |
| 94 | jmp setup_car_mtrr |
| 95 | |
| 96 | no_bootguard: |
Arthur Heymans | c4772b9 | 2019-04-14 18:38:35 +0200 | [diff] [blame] | 97 | movl $no_reset, %esp /* return address */ |
| 98 | jmp check_mtrr /* Check if CPU properly reset */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 99 | |
| 100 | no_reset: |
| 101 | post_code(0x21) |
| 102 | |
| 103 | /* Clear/disable fixed MTRRs */ |
| 104 | mov $fixed_mtrr_list_size, %ebx |
| 105 | xor %eax, %eax |
| 106 | xor %edx, %edx |
| 107 | |
| 108 | clear_fixed_mtrr: |
| 109 | add $-2, %ebx |
| 110 | movzwl fixed_mtrr_list(%ebx), %ecx |
| 111 | wrmsr |
| 112 | jnz clear_fixed_mtrr |
| 113 | |
| 114 | post_code(0x22) |
| 115 | |
Arthur Heymans | c57d303 | 2021-06-16 09:56:26 +0200 | [diff] [blame] | 116 | /* Figure out how many MTRRs we have, and clear them out */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 117 | mov $MTRR_CAP_MSR, %ecx |
| 118 | rdmsr |
| 119 | movzb %al, %ebx /* Number of variable MTRRs */ |
| 120 | mov $MTRR_PHYS_BASE(0), %ecx |
| 121 | xor %eax, %eax |
| 122 | xor %edx, %edx |
| 123 | |
| 124 | clear_var_mtrr: |
| 125 | wrmsr |
| 126 | inc %ecx |
| 127 | wrmsr |
| 128 | inc %ecx |
| 129 | dec %ebx |
| 130 | jnz clear_var_mtrr |
| 131 | |
| 132 | post_code(0x23) |
| 133 | |
| 134 | /* Configure default memory type to uncacheable (UC) */ |
| 135 | mov $MTRR_DEF_TYPE_MSR, %ecx |
| 136 | rdmsr |
| 137 | /* Clear enable bits and set default type to UC. */ |
| 138 | and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ |
| 139 | MTRR_DEF_TYPE_FIX_EN), %eax |
| 140 | wrmsr |
| 141 | |
Arthur Heymans | 481c52d | 2019-11-08 17:05:04 +0100 | [diff] [blame] | 142 | setup_car_mtrr: |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 143 | /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB |
| 144 | * based on the physical address size supported for this processor |
| 145 | * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] |
| 146 | * |
| 147 | * Examples: |
| 148 | * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing |
| 149 | * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing |
| 150 | */ |
| 151 | |
Elyes HAOUAS | 05498a2 | 2018-05-28 16:26:43 +0200 | [diff] [blame] | 152 | movl $0x80000008, %eax /* Address sizes leaf */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 153 | cpuid |
| 154 | sub $32, %al |
| 155 | movzx %al, %eax |
| 156 | xorl %esi, %esi |
| 157 | bts %eax, %esi |
| 158 | dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ |
| 159 | |
| 160 | post_code(0x24) |
| 161 | |
| 162 | #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) |
Arthur Heymans | 64c9c6d | 2019-11-25 09:45:40 +0100 | [diff] [blame] | 163 | find_free_mtrr |
| 164 | test %ebx, %ebx |
| 165 | jz .halt_forever |
| 166 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 167 | /* Configure CAR region as write-back (WB) */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 168 | mov $CONFIG_DCACHE_RAM_BASE, %eax |
| 169 | or $MTRR_TYPE_WRBACK, %eax |
| 170 | xor %edx,%edx |
| 171 | wrmsr |
| 172 | |
| 173 | /* Configure the MTRR mask for the size region */ |
Arthur Heymans | 64c9c6d | 2019-11-25 09:45:40 +0100 | [diff] [blame] | 174 | inc %ecx |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 175 | mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ |
| 176 | dec %eax |
| 177 | not %eax |
| 178 | or $MTRR_PHYS_MASK_VALID, %eax |
| 179 | movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ |
| 180 | wrmsr |
| 181 | #elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ |
Arthur Heymans | 64c9c6d | 2019-11-25 09:45:40 +0100 | [diff] [blame] | 182 | find_free_mtrr |
| 183 | test %ebx, %ebx |
| 184 | jz .halt_forever |
| 185 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 186 | /* Configure CAR region as write-back (WB) */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 187 | mov $CONFIG_DCACHE_RAM_BASE, %eax |
| 188 | or $MTRR_TYPE_WRBACK, %eax |
| 189 | xor %edx,%edx |
| 190 | wrmsr |
| 191 | |
Arthur Heymans | 64c9c6d | 2019-11-25 09:45:40 +0100 | [diff] [blame] | 192 | incl %ecx |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 193 | mov $(512 * KiB), %eax /* size mask */ |
| 194 | dec %eax |
| 195 | not %eax |
| 196 | or $MTRR_PHYS_MASK_VALID, %eax |
| 197 | movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ |
| 198 | wrmsr |
| 199 | |
Arthur Heymans | 64c9c6d | 2019-11-25 09:45:40 +0100 | [diff] [blame] | 200 | find_free_mtrr |
| 201 | test %ebx, %ebx |
| 202 | jz .halt_forever |
| 203 | 1: |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 204 | mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax |
| 205 | or $MTRR_TYPE_WRBACK, %eax |
| 206 | xor %edx,%edx |
| 207 | wrmsr |
| 208 | |
Arthur Heymans | 64c9c6d | 2019-11-25 09:45:40 +0100 | [diff] [blame] | 209 | incl %ecx |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 210 | mov $(256 * KiB), %eax /* size mask */ |
| 211 | dec %eax |
| 212 | not %eax |
| 213 | or $MTRR_PHYS_MASK_VALID, %eax |
| 214 | movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ |
| 215 | wrmsr |
| 216 | #else |
| 217 | #error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" |
| 218 | #endif |
| 219 | post_code(0x25) |
| 220 | |
Arthur Heymans | cd96fed5 | 2021-06-23 10:48:28 +0200 | [diff] [blame] | 221 | is_bootguard_nem |
Arthur Heymans | 481c52d | 2019-11-08 17:05:04 +0100 | [diff] [blame] | 222 | jz no_bootguard_car_continue |
| 223 | |
Arthur Heymans | 5cb24d4 | 2021-06-23 13:17:33 +0200 | [diff] [blame] | 224 | /* |
| 225 | * With Bootguard some RO caching of the flash is already set up by |
| 226 | * the ACM. It looks like in such a setup 'clear_car' will not properly fill |
| 227 | * the cachelines. Fill all the CAR cachelines explicitly using sfence. |
| 228 | * This assumes 64 bytes cachelines. |
| 229 | */ |
| 230 | movl $CONFIG_DCACHE_RAM_BASE, %edi |
| 231 | movl $CONFIG_DCACHE_RAM_SIZE, %ecx |
| 232 | shr $0x06, %ecx |
| 233 | xor %eax, %eax |
| 234 | |
| 235 | 1: |
| 236 | movl %eax, (%edi) |
| 237 | sfence |
| 238 | add $64, %edi |
| 239 | loop 1b |
| 240 | |
Arthur Heymans | 481c52d | 2019-11-08 17:05:04 +0100 | [diff] [blame] | 241 | clear_car |
| 242 | |
| 243 | jmp car_init_done |
| 244 | |
| 245 | no_bootguard_car_continue: |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 246 | /* Enable variable MTRRs */ |
| 247 | mov $MTRR_DEF_TYPE_MSR, %ecx |
| 248 | rdmsr |
| 249 | or $MTRR_DEF_TYPE_EN, %eax |
| 250 | wrmsr |
| 251 | |
| 252 | /* Enable caching */ |
| 253 | mov %cr0, %eax |
| 254 | and $~(CR0_CD | CR0_NW), %eax |
| 255 | invd |
| 256 | mov %eax, %cr0 |
| 257 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 258 | #if CONFIG(INTEL_CAR_NEM) |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 259 | jmp car_nem |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 260 | #elif CONFIG(INTEL_CAR_CQOS) |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 261 | jmp car_cqos |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 262 | #elif CONFIG(INTEL_CAR_NEM_ENHANCED) |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 263 | jmp car_nem_enhanced |
| 264 | #else |
| 265 | jmp .halt_forever /* In case nothing has selected */ |
| 266 | #endif |
| 267 | |
| 268 | .global car_init_done |
| 269 | car_init_done: |
| 270 | |
| 271 | post_code(0x29) |
| 272 | |
| 273 | /* Setup bootblock stack */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 274 | mov $_ecar_stack, %esp |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 275 | |
Aaron Durbin | 028e18f | 2017-06-23 11:14:58 -0500 | [diff] [blame] | 276 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 277 | the two pushes below. */ |
| 278 | andl $0xfffffff0, %esp |
Patrick Rudolph | 2b77112 | 2020-11-30 13:52:42 +0100 | [diff] [blame] | 279 | |
| 280 | #if ENV_X86_64 |
| 281 | #include <cpu/x86/64bit/entry64.inc> |
| 282 | movd %mm2, %rdi |
| 283 | shlq $32, %rdi |
| 284 | movd %mm1, %rsi |
| 285 | or %rsi, %rdi |
| 286 | movd %mm0, %rsi |
| 287 | #else |
Aaron Durbin | 028e18f | 2017-06-23 11:14:58 -0500 | [diff] [blame] | 288 | sub $8, %esp |
| 289 | |
Subrata Banik | 5885ffe | 2019-11-14 11:08:51 +0530 | [diff] [blame] | 290 | /* push TSC value to stack */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 291 | movd %mm2, %eax |
| 292 | pushl %eax /* tsc[63:32] */ |
| 293 | movd %mm1, %eax |
Elyes HAOUAS | 05498a2 | 2018-05-28 16:26:43 +0200 | [diff] [blame] | 294 | pushl %eax /* tsc[31:0] */ |
Patrick Rudolph | 2b77112 | 2020-11-30 13:52:42 +0100 | [diff] [blame] | 295 | #endif |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 296 | |
| 297 | before_carstage: |
| 298 | post_code(0x2A) |
| 299 | |
| 300 | call bootblock_c_entry |
| 301 | /* Never reached */ |
| 302 | |
| 303 | .halt_forever: |
| 304 | post_code(POST_DEAD_CODE) |
| 305 | hlt |
| 306 | jmp .halt_forever |
| 307 | |
| 308 | fixed_mtrr_list: |
| 309 | .word MTRR_FIX_64K_00000 |
| 310 | .word MTRR_FIX_16K_80000 |
| 311 | .word MTRR_FIX_16K_A0000 |
| 312 | .word MTRR_FIX_4K_C0000 |
| 313 | .word MTRR_FIX_4K_C8000 |
| 314 | .word MTRR_FIX_4K_D0000 |
| 315 | .word MTRR_FIX_4K_D8000 |
| 316 | .word MTRR_FIX_4K_E0000 |
| 317 | .word MTRR_FIX_4K_E8000 |
| 318 | .word MTRR_FIX_4K_F0000 |
| 319 | .word MTRR_FIX_4K_F8000 |
| 320 | fixed_mtrr_list_size = . - fixed_mtrr_list |
| 321 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 322 | #if CONFIG(INTEL_CAR_NEM) |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 323 | .global car_nem |
| 324 | car_nem: |
| 325 | /* Disable cache eviction (setup stage) */ |
| 326 | mov $MSR_EVICT_CTL, %ecx |
| 327 | rdmsr |
| 328 | or $0x1, %eax |
| 329 | wrmsr |
| 330 | |
| 331 | post_code(0x26) |
| 332 | |
Arthur Heymans | 99a48bc | 2019-11-25 09:56:20 +0100 | [diff] [blame] | 333 | clear_car |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 334 | |
| 335 | post_code(0x27) |
| 336 | |
| 337 | /* Disable cache eviction (run stage) */ |
| 338 | mov $MSR_EVICT_CTL, %ecx |
| 339 | rdmsr |
| 340 | or $0x2, %eax |
| 341 | wrmsr |
| 342 | |
| 343 | post_code(0x28) |
| 344 | |
| 345 | jmp car_init_done |
| 346 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 347 | #elif CONFIG(INTEL_CAR_CQOS) |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 348 | .global car_cqos |
| 349 | car_cqos: |
| 350 | /* |
Naresh G Solanki | f329f0c | 2017-09-27 14:21:18 +0530 | [diff] [blame] | 351 | * Create CBM_LEN_MASK based on CBM_LEN |
| 352 | * Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0] |
| 353 | */ |
| 354 | mov $0x10, %eax |
| 355 | mov $0x2, %ecx |
| 356 | cpuid |
| 357 | and $0x1F, %eax |
| 358 | add $1, %al |
| 359 | |
| 360 | mov $1, %ebx |
| 361 | mov %al, %cl |
| 362 | shl %cl, %ebx |
| 363 | sub $1, %ebx |
| 364 | |
| 365 | /* Store the CBM_LEN_MASK in mm3 for later use. */ |
| 366 | movd %ebx, %mm3 |
| 367 | |
| 368 | /* |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 369 | * Disable both L1 and L2 prefetcher. For yet-to-understood reason, |
| 370 | * prefetchers slow down filling cache with rep stos in CQOS mode. |
| 371 | */ |
| 372 | mov $MSR_PREFETCH_CTL, %ecx |
| 373 | rdmsr |
| 374 | or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax |
| 375 | wrmsr |
| 376 | |
| 377 | #if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE) |
| 378 | /* |
| 379 | * If CAR size is set to full L2 size, mask is calculated as all-zeros. |
| 380 | * This is not supported by the CPU/uCode. |
| 381 | */ |
| 382 | #error "CQOS CAR may not use whole L2 cache area" |
| 383 | #endif |
| 384 | |
| 385 | /* Calculate how many bits to be used for CAR */ |
| 386 | xor %edx, %edx |
| 387 | mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */ |
| 388 | mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */ |
| 389 | div %ecx /* result is in eax */ |
| 390 | mov %eax, %ecx /* save to ecx */ |
| 391 | mov $1, %ebx |
| 392 | shl %cl, %ebx |
| 393 | sub $1, %ebx /* resulting mask is is in ebx */ |
| 394 | |
| 395 | /* Set this mask for initial cache fill */ |
| 396 | mov $MSR_L2_QOS_MASK(0), %ecx |
| 397 | rdmsr |
Naresh G Solanki | f329f0c | 2017-09-27 14:21:18 +0530 | [diff] [blame] | 398 | mov %ebx, %eax |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 399 | wrmsr |
| 400 | |
| 401 | /* Set CLOS selector to 0 */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 402 | mov $IA32_PQR_ASSOC, %ecx |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 403 | rdmsr |
| 404 | and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ |
| 405 | wrmsr |
| 406 | |
| 407 | /* We will need to block CAR region from evicts */ |
| 408 | mov $MSR_L2_QOS_MASK(1), %ecx |
| 409 | rdmsr |
| 410 | /* Invert bits that are to be used for cache */ |
Naresh G Solanki | f329f0c | 2017-09-27 14:21:18 +0530 | [diff] [blame] | 411 | mov %ebx, %eax |
| 412 | xor $~0, %eax /* invert 32 bits */ |
| 413 | |
| 414 | /* |
| 415 | * Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit |
| 416 | * Mask Length. |
| 417 | */ |
| 418 | movd %mm3, %ebx |
| 419 | and %ebx, %eax |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 420 | wrmsr |
| 421 | |
| 422 | post_code(0x26) |
| 423 | |
Arthur Heymans | 99a48bc | 2019-11-25 09:56:20 +0100 | [diff] [blame] | 424 | clear_car |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 425 | |
| 426 | post_code(0x27) |
| 427 | |
| 428 | /* Cache is populated. Use mask 1 that will block evicts */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 429 | mov $IA32_PQR_ASSOC, %ecx |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 430 | rdmsr |
| 431 | and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ |
| 432 | or $1, %edx /* select mask 1 */ |
| 433 | wrmsr |
| 434 | |
| 435 | /* Enable prefetchers */ |
| 436 | mov $MSR_PREFETCH_CTL, %ecx |
| 437 | rdmsr |
| 438 | and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax |
| 439 | wrmsr |
| 440 | |
| 441 | post_code(0x28) |
| 442 | |
| 443 | jmp car_init_done |
| 444 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 445 | #elif CONFIG(INTEL_CAR_NEM_ENHANCED) |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 446 | .global car_nem_enhanced |
| 447 | car_nem_enhanced: |
| 448 | /* Disable cache eviction (setup stage) */ |
| 449 | mov $MSR_EVICT_CTL, %ecx |
| 450 | rdmsr |
| 451 | or $0x1, %eax |
| 452 | wrmsr |
| 453 | post_code(0x26) |
| 454 | |
| 455 | /* Create n-way set associativity of cache */ |
| 456 | xorl %edi, %edi |
| 457 | find_llc_subleaf: |
| 458 | movl %edi, %ecx |
| 459 | movl $0x04, %eax |
| 460 | cpuid |
| 461 | inc %edi |
| 462 | and $0xe0, %al /* EAX[7:5] = Cache Level */ |
| 463 | cmp $0x60, %al /* Check to see if it is LLC */ |
| 464 | jnz find_llc_subleaf |
| 465 | |
| 466 | /* |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 467 | * Calculate the total LLC size |
| 468 | * (Line_Size + 1) * (Sets + 1) * (Partitions + 1) * (Ways + 1) |
| 469 | * (EBX[11:0] + 1) * (ECX + 1) * (EBX[21:12] + 1) * EBX[31:22] + 1) |
| 470 | */ |
| 471 | |
| 472 | mov %ebx, %eax |
| 473 | and $0xFFF, %eax |
| 474 | inc %eax |
| 475 | inc %ecx |
| 476 | mul %ecx |
| 477 | mov %eax, %ecx |
| 478 | mov %ebx, %eax |
| 479 | shr $12, %eax |
| 480 | and $0x3FF, %eax |
| 481 | inc %eax |
| 482 | mul %ecx |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 483 | shr $22, %ebx |
| 484 | inc %ebx |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 485 | mov %ebx, %edx |
| 486 | mul %ebx /* eax now holds total LLC size */ |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 487 | |
| 488 | /* |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 489 | * The number of the ways that we want to protect from eviction |
| 490 | * can be calculated as RW data stack size / way size where way |
| 491 | * size is Total LLC size / Total number of LLC ways. |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 492 | */ |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 493 | div %ebx /* way size */ |
| 494 | mov %eax, %ecx |
| 495 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 496 | /* |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 497 | * Check if way size if bigger than the cache ram size. |
| 498 | * Then we need to allocate just one way for non-eviction |
| 499 | * of RW data. |
| 500 | */ |
Subrata Banik | 0603902 | 2021-03-09 14:40:39 +0530 | [diff] [blame] | 501 | movl $0x01, %eax |
| 502 | cmp $CONFIG_DCACHE_RAM_SIZE, %ecx |
| 503 | jnc set_eviction_mask |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 504 | |
| 505 | /* |
| 506 | * RW data size / way size is equal to number of |
| 507 | * ways to be configured for non-eviction |
| 508 | */ |
Subrata Banik | 0603902 | 2021-03-09 14:40:39 +0530 | [diff] [blame] | 509 | mov $CONFIG_DCACHE_RAM_SIZE, %eax |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 510 | div %ecx |
| 511 | mov %eax, %ecx |
| 512 | movl $0x01, %eax |
| 513 | shl %cl, %eax |
| 514 | subl $0x01, %eax |
| 515 | |
| 516 | set_eviction_mask: |
Shreesh Chhabbi | 860c684 | 2020-12-03 15:06:20 -0800 | [diff] [blame] | 517 | mov %ebx, %ecx /* back up number of ways */ |
| 518 | mov %eax, %ebx /* back up the non-eviction mask*/ |
| 519 | #if CONFIG(CAR_HAS_SF_MASKS) |
| 520 | mov %ecx, %edi /* use number of ways to prepare SF mask */ |
| 521 | /* |
| 522 | * SF mask is programmed with the double number of bits than |
| 523 | * the number of ways |
| 524 | */ |
| 525 | mov $0x01, %eax |
| 526 | shl %cl, %eax |
| 527 | shl %cl, %eax |
| 528 | subl $0x01, %eax /* contains SF mask */ |
| 529 | /* |
| 530 | * Program MSR 0x1891 IA32_CR_SF_QOS_MASK_1 with |
| 531 | * total number of LLC ways |
| 532 | */ |
| 533 | movl $IA32_CR_SF_QOS_MASK_1, %ecx |
| 534 | xorl %edx, %edx |
| 535 | wrmsr |
| 536 | mov %edi, %ecx /* restore number of ways */ |
| 537 | #endif |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 538 | /* |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 539 | * Program MSR 0xC91 IA32_L3_MASK_1 |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 540 | * This MSR contain one bit per each way of LLC |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 541 | * - If this bit is '0' - the way is protected from eviction |
| 542 | * - If this bit is '1' - the way is not protected from eviction |
| 543 | */ |
Subrata Banik | 0603902 | 2021-03-09 14:40:39 +0530 | [diff] [blame] | 544 | mov $0x1, %eax |
| 545 | shl %cl, %eax |
| 546 | subl $0x01, %eax |
| 547 | mov %eax, %ecx |
| 548 | mov %ebx, %eax |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 549 | |
| 550 | xor $~0, %eax /* invert 32 bits */ |
| 551 | and %ecx, %eax |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 552 | movl $IA32_L3_MASK_1, %ecx |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 553 | xorl %edx, %edx |
| 554 | wrmsr |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 555 | /* |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 556 | * Program MSR 0xC92 IA32_L3_MASK_2 |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 557 | * This MSR contain one bit per each way of LLC |
| 558 | * - If this bit is '0' - the way is protected from eviction |
| 559 | * - If this bit is '1' - the way is not protected from eviction |
| 560 | */ |
| 561 | mov %ebx, %eax |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 562 | movl $IA32_L3_MASK_2, %ecx |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 563 | xorl %edx, %edx |
| 564 | wrmsr |
| 565 | /* |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 566 | * Set IA32_PQR_ASSOC |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 567 | * |
| 568 | * Possible values: |
| 569 | * 0: Default value, no way mask should be applied |
| 570 | * 1: Apply way mask 1 to LLC |
| 571 | * 2: Apply way mask 2 to LLC |
| 572 | * 3: Shouldn't be use in NEM Mode |
| 573 | */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 574 | movl $IA32_PQR_ASSOC, %ecx |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 575 | xorl %eax, %eax |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 576 | xorl %edx, %edx |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 577 | #if CONFIG(COS_MAPPED_TO_MSB) |
| 578 | movl $0x02, %edx |
| 579 | #else |
| 580 | movl $0x02, %eax |
| 581 | #endif |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 582 | wrmsr |
Arthur Heymans | 99a48bc | 2019-11-25 09:56:20 +0100 | [diff] [blame] | 583 | |
| 584 | clear_car |
| 585 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 586 | /* |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 587 | * Set IA32_PQR_ASSOC |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 588 | * At this stage we apply LLC_WAY_MASK_1 to the cache. |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 589 | */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 590 | movl $IA32_PQR_ASSOC, %ecx |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 591 | xorl %eax, %eax |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 592 | xorl %edx, %edx |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame] | 593 | #if CONFIG(COS_MAPPED_TO_MSB) |
| 594 | movl $0x01, %edx |
| 595 | #else |
| 596 | movl $0x01, %eax |
| 597 | #endif |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 598 | wrmsr |
| 599 | |
| 600 | post_code(0x27) |
| 601 | /* |
| 602 | * Enable No-Eviction Mode Run State by setting |
| 603 | * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. |
| 604 | */ |
| 605 | |
| 606 | movl $MSR_EVICT_CTL, %ecx |
| 607 | rdmsr |
| 608 | orl $0x02, %eax |
| 609 | wrmsr |
| 610 | |
| 611 | post_code(0x28) |
| 612 | |
| 613 | jmp car_init_done |
| 614 | #endif |