| commit | c57d303f9cf18574370878392986224b57595818 | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Wed Jun 16 09:56:26 2021 +0200 |
| committer | Werner Zeh <werner.zeh@siemens.com> | Fri Jun 18 04:40:38 2021 +0000 |
| tree | 419e210a911036dbc636121500257968750b7b2c | |
| parent | 0faba3cf237df532dce8f61ca6a765c335093bbf [diff] [blame] |
soc/intel/car/cache_as_ram.S: Fix typo in comment Change-Id: Ia91dbda44f60388324cf58dbccdbd2172dbff21d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55561 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0d9eb67..3817fa5 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -36,7 +36,7 @@ post_code(0x22) - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */