Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | Public include file for PageTableLib library. |
| 3 | |
| 4 | Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 6 | |
| 7 | **/ |
| 8 | |
| 9 | #ifndef PAGE_TABLE_LIB_H_ |
| 10 | #define PAGE_TABLE_LIB_H_ |
| 11 | |
| 12 | typedef union { |
| 13 | struct { |
| 14 | UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory |
| 15 | UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write |
| 16 | UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User |
| 17 | UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching |
| 18 | UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached |
| 19 | UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU) |
| 20 | UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU) |
| 21 | UINT64 Pat : 1; // PAT |
| 22 | |
| 23 | UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1) |
| 24 | UINT64 Reserved1 : 3; // Ignored |
| 25 | |
| 26 | UINT64 PageTableBaseAddress : 40; // Page Table Base Address |
| 27 | UINT64 Reserved2 : 7; // Ignored |
| 28 | UINT64 ProtectionKey : 4; // Protection key |
| 29 | UINT64 Nx : 1; // No Execute bit |
| 30 | } Bits; |
| 31 | UINT64 Uint64; |
| 32 | } IA32_MAP_ATTRIBUTE; |
| 33 | |
| 34 | #define IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK 0xFFFFFFFFFF000ull |
| 35 | #define IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK) |
| 36 | #define IA32_MAP_ATTRIBUTE_ATTRIBUTES(pa) ((pa)->Uint64 & ~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK) |
| 37 | |
| 38 | // |
| 39 | // Below enum follows "4.1.1 Four Paging Modes" in Chapter 4 Paging of SDM Volume 3. |
| 40 | // Page1GB is only supported in 4-level and 5-level. |
| 41 | // |
| 42 | typedef enum { |
| 43 | Paging32bit, |
| 44 | |
| 45 | // |
| 46 | // High byte in paging mode indicates the max levels of the page table. |
| 47 | // Low byte in paging mode indicates the max level that can be a leaf entry. |
| 48 | // |
| 49 | PagingPae = 0x0302, |
| 50 | |
| 51 | Paging4Level = 0x0402, |
| 52 | Paging4Level1GB = 0x0403, |
| 53 | |
| 54 | Paging5Level = 0x0502, |
| 55 | Paging5Level1GB = 0x0503, |
| 56 | |
| 57 | PagingModeMax |
| 58 | } PAGING_MODE; |
| 59 | |
| 60 | /** |
| 61 | Create or update page table to map [LinearAddress, LinearAddress + Length) with specified attribute. |
| 62 | |
| 63 | @param[in, out] PageTable The pointer to the page table to update, or pointer to NULL if a new page table is to be created. |
| 64 | @param[in] PagingMode The paging mode. |
| 65 | @param[in] Buffer The free buffer to be used for page table creation/updating. |
| 66 | @param[in, out] BufferSize The buffer size. |
| 67 | On return, the remaining buffer size. |
| 68 | The free buffer is used from the end so caller can supply the same Buffer pointer with an updated |
| 69 | BufferSize in the second call to this API. |
| 70 | @param[in] LinearAddress The start of the linear address range. |
| 71 | @param[in] Length The length of the linear address range. |
| 72 | @param[in] Attribute The attribute of the linear address range. |
| 73 | All non-reserved fields in IA32_MAP_ATTRIBUTE are supported to set in the page table. |
| 74 | Page table entries that map the linear address range are reset to 0 before set to the new attribute |
| 75 | when a new physical base address is set. |
| 76 | @param[in] Mask The mask used for attribute. The corresponding field in Attribute is ignored if that in Mask is 0. |
| 77 | |
| 78 | @retval RETURN_UNSUPPORTED PagingMode is not supported. |
| 79 | @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Mask is NULL. |
| 80 | @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. |
| 81 | @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table creation/updating. |
| 82 | BufferSize is updated to indicate the expected buffer size. |
| 83 | Caller may still get RETURN_BUFFER_TOO_SMALL with the new BufferSize. |
| 84 | @retval RETURN_SUCCESS PageTable is created/updated successfully. |
| 85 | **/ |
| 86 | RETURN_STATUS |
| 87 | EFIAPI |
| 88 | PageTableMap ( |
| 89 | IN OUT UINTN *PageTable OPTIONAL, |
| 90 | IN PAGING_MODE PagingMode, |
| 91 | IN VOID *Buffer, |
| 92 | IN OUT UINTN *BufferSize, |
| 93 | IN UINT64 LinearAddress, |
| 94 | IN UINT64 Length, |
| 95 | IN IA32_MAP_ATTRIBUTE *Attribute, |
| 96 | IN IA32_MAP_ATTRIBUTE *Mask |
| 97 | ); |
| 98 | |
| 99 | typedef struct { |
| 100 | UINT64 LinearAddress; |
| 101 | UINT64 Length; |
| 102 | IA32_MAP_ATTRIBUTE Attribute; |
| 103 | } IA32_MAP_ENTRY; |
| 104 | |
| 105 | /** |
| 106 | Parse page table. |
| 107 | |
| 108 | @param[in] PageTable Pointer to the page table. |
| 109 | @param[in] PagingMode The paging mode. |
| 110 | @param[out] Map Return an array that describes multiple linear address ranges. |
| 111 | @param[in, out] MapCount On input, the maximum number of entries that Map can hold. |
| 112 | On output, the number of entries in Map. |
| 113 | |
| 114 | @retval RETURN_UNSUPPORTED PageLevel is not 5 or 4. |
| 115 | @retval RETURN_INVALID_PARAMETER MapCount is NULL. |
| 116 | @retval RETURN_INVALID_PARAMETER *MapCount is not 0 but Map is NULL. |
| 117 | @retval RETURN_BUFFER_TOO_SMALL *MapCount is too small. |
| 118 | @retval RETURN_SUCCESS Page table is parsed successfully. |
| 119 | **/ |
| 120 | RETURN_STATUS |
| 121 | EFIAPI |
| 122 | PageTableParse ( |
| 123 | IN UINTN PageTable, |
| 124 | IN PAGING_MODE PagingMode, |
| 125 | IN IA32_MAP_ENTRY *Map, |
| 126 | IN OUT UINTN *MapCount |
| 127 | ); |
| 128 | |
| 129 | #endif |