Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | Definitions for CPU S3 data. |
| 3 | |
| 4 | Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.<BR> |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 6 | |
| 7 | **/ |
| 8 | |
| 9 | #ifndef _ACPI_CPU_DATA_H_ |
| 10 | #define _ACPI_CPU_DATA_H_ |
| 11 | |
| 12 | // |
| 13 | // This macro definition is used to fix incompatibility issue caused by |
| 14 | // ACPI_CPU_DATA structure update. It will be removed after all the platform |
| 15 | // code uses new ACPI_CPU_DATA structure. |
| 16 | // |
| 17 | #define ACPI_CPU_DATA_STRUCTURE_UPDATE |
| 18 | |
| 19 | // |
| 20 | // Register types in register table |
| 21 | // |
| 22 | typedef enum { |
| 23 | Msr, |
| 24 | ControlRegister, |
| 25 | MemoryMapped, |
| 26 | CacheControl, |
| 27 | |
| 28 | // |
| 29 | // Semaphore type used to control the execute sequence of the Msr. |
| 30 | // It will be insert between two Msr which has execute dependence. |
| 31 | // |
| 32 | Semaphore, |
| 33 | InvalidReg |
| 34 | } REGISTER_TYPE; |
| 35 | |
| 36 | // |
| 37 | // Describe the dependency type for different features. |
| 38 | // The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is Semaphore. |
| 39 | // |
| 40 | typedef enum { |
| 41 | NoneDepType, |
| 42 | ThreadDepType, |
| 43 | CoreDepType, |
| 44 | PackageDepType, |
| 45 | InvalidDepType |
| 46 | } CPU_FEATURE_DEPENDENCE_TYPE; |
| 47 | |
| 48 | // |
| 49 | // CPU information. |
| 50 | // |
| 51 | typedef struct { |
| 52 | // |
| 53 | // Record the package count in this CPU. |
| 54 | // |
| 55 | UINT32 PackageCount; |
| 56 | // |
| 57 | // Record the max core count in this CPU. |
| 58 | // Different packages may have different core count, this value |
| 59 | // save the max core count in all the packages. |
| 60 | // |
| 61 | UINT32 MaxCoreCount; |
| 62 | // |
| 63 | // Record the max thread count in this CPU. |
| 64 | // Different cores may have different thread count, this value |
| 65 | // save the max thread count in all the cores. |
| 66 | // |
| 67 | UINT32 MaxThreadCount; |
| 68 | // |
| 69 | // This field points to an array. |
| 70 | // This array saves thread count (type UINT32) of each package. |
| 71 | // The array has PackageCount elements. |
| 72 | // |
| 73 | // If the platform does not support MSR setting at S3 resume, and |
| 74 | // therefore it doesn't need the dependency semaphores, it should set |
| 75 | // this field to 0. |
| 76 | // |
| 77 | EFI_PHYSICAL_ADDRESS ThreadCountPerPackage; |
| 78 | // |
| 79 | // This field points to an array. |
| 80 | // This array saves thread count (type UINT8) of each core. |
| 81 | // The array has PackageCount * MaxCoreCount elements. |
| 82 | // |
| 83 | // If the platform does not support MSR setting at S3 resume, and |
| 84 | // therefore it doesn't need the dependency semaphores, it should set |
| 85 | // this field to 0. |
| 86 | // |
| 87 | EFI_PHYSICAL_ADDRESS ThreadCountPerCore; |
| 88 | } CPU_STATUS_INFORMATION; |
| 89 | |
| 90 | // |
| 91 | // Element of register table entry |
| 92 | // |
| 93 | typedef struct { |
| 94 | REGISTER_TYPE RegisterType; // offset 0 - 3 |
| 95 | UINT32 Index; // offset 4 - 7 |
| 96 | UINT8 ValidBitStart; // offset 8 |
| 97 | UINT8 ValidBitLength; // offset 9 |
| 98 | BOOLEAN TestThenWrite; // offset 10 |
| 99 | UINT8 Reserved1; // offset 11 |
| 100 | UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped |
| 101 | UINT64 Value; // offset 16-23 |
| 102 | } CPU_REGISTER_TABLE_ENTRY; |
| 103 | |
| 104 | // |
| 105 | // Register table definition, including current table length, |
| 106 | // allocated size of this table, and pointer to the list of table entries. |
| 107 | // |
| 108 | typedef struct { |
| 109 | // |
| 110 | // The number of valid entries in the RegisterTableEntry buffer |
| 111 | // |
| 112 | UINT32 TableLength; |
| 113 | UINT32 NumberBeforeReset; |
| 114 | // |
| 115 | // The size, in bytes, of the RegisterTableEntry buffer |
| 116 | // |
| 117 | UINT32 AllocatedSize; |
| 118 | // |
| 119 | // The initial APIC ID of the CPU this register table applies to |
| 120 | // |
| 121 | UINT32 InitialApicId; |
| 122 | // |
| 123 | // Physical address of CPU_REGISTER_TABLE_ENTRY structures. |
| 124 | // |
| 125 | EFI_PHYSICAL_ADDRESS RegisterTableEntry; |
| 126 | } CPU_REGISTER_TABLE; |
| 127 | |
| 128 | // |
| 129 | // Data structure that is used for CPU feature initialization during ACPI S3 |
| 130 | // resume. |
| 131 | // |
| 132 | typedef struct { |
| 133 | // |
| 134 | // Physical address of an array of CPU_REGISTER_TABLE structures, with |
| 135 | // NumberOfCpus entries. If a register table is not required, then the |
| 136 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0. |
| 137 | // If TableLength is > 0, then elements of RegisterTableEntry are used to |
| 138 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume, |
| 139 | // before SMBASE relocation is performed. |
| 140 | // If a register table is not required for any one of the CPUs, then |
| 141 | // PreSmmInitRegisterTable may be set to 0. |
| 142 | // |
| 143 | EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable; |
| 144 | // |
| 145 | // Physical address of an array of CPU_REGISTER_TABLE structures, with |
| 146 | // NumberOfCpus entries. If a register table is not required, then the |
| 147 | // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0. |
| 148 | // If TableLength is > 0, then elements of RegisterTableEntry are used to |
| 149 | // initialize the CPU that matches InitialApicId, during an ACPI S3 resume, |
| 150 | // after SMBASE relocation is performed. |
| 151 | // If a register table is not required for any one of the CPUs, then |
| 152 | // RegisterTable may be set to 0. |
| 153 | // |
| 154 | EFI_PHYSICAL_ADDRESS RegisterTable; |
| 155 | // |
| 156 | // CPU information which is required when set the register table. |
| 157 | // |
| 158 | CPU_STATUS_INFORMATION CpuStatus; |
| 159 | // |
| 160 | // Location info for each AP. |
| 161 | // It points to an array which saves all APs location info. |
| 162 | // The array count is the AP count in this CPU. |
| 163 | // |
| 164 | // If the platform does not support MSR setting at S3 resume, and |
| 165 | // therefore it doesn't need the dependency semaphores, it should set |
| 166 | // this field to 0. |
| 167 | // |
| 168 | EFI_PHYSICAL_ADDRESS ApLocation; |
| 169 | } CPU_FEATURE_INIT_DATA; |
| 170 | |
| 171 | // |
| 172 | // Data structure that is required for ACPI S3 resume. The PCD |
| 173 | // PcdCpuS3DataAddress must be set to the physical address where this structure |
| 174 | // is allocated |
| 175 | // |
| 176 | typedef struct { |
| 177 | // |
| 178 | // Physical address of 4KB buffer allocated below 1MB from memory of type |
| 179 | // EfiReservedMemoryType. The buffer is not required to be initialized, but |
| 180 | // it is recommended that the buffer be zero-filled. This buffer is used to |
| 181 | // wake APs during an ACPI S3 resume. |
| 182 | // |
| 183 | EFI_PHYSICAL_ADDRESS StartupVector; |
| 184 | // |
| 185 | // Physical address of structure of type IA32_DESCRIPTOR. The |
| 186 | // IA32_DESCRIPTOR structure provides the base address and length of a GDT |
| 187 | // The GDT must be filled in with the GDT contents that are |
| 188 | // used during an ACPI S3 resume. This is typically the contents of the GDT |
| 189 | // used by the boot processor when the platform is booted. |
| 190 | // |
| 191 | EFI_PHYSICAL_ADDRESS GdtrProfile; |
| 192 | // |
| 193 | // Physical address of structure of type IA32_DESCRIPTOR. The |
| 194 | // IA32_DESCRIPTOR structure provides the base address and length of an IDT. |
| 195 | // The IDT must be filled in with the IDT contents that are |
| 196 | // used during an ACPI S3 resume. This is typically the contents of the IDT |
| 197 | // used by the boot processor when the platform is booted. |
| 198 | // |
| 199 | EFI_PHYSICAL_ADDRESS IdtrProfile; |
| 200 | // |
| 201 | // Physical address of a buffer that is used as stacks during ACPI S3 resume. |
| 202 | // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This |
| 203 | // structure must be allocated from memory of type EfiACPIMemoryNVS. |
| 204 | // |
| 205 | EFI_PHYSICAL_ADDRESS StackAddress; |
| 206 | // |
| 207 | // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume. |
| 208 | // |
| 209 | UINT32 StackSize; |
| 210 | // |
| 211 | // The number of CPUs. If a platform does not support hot plug CPUs, then |
| 212 | // this is the number of CPUs detected when the platform is booted, regardless |
| 213 | // of being enabled or disabled. If a platform does support hot plug CPUs, |
| 214 | // then this is the maximum number of CPUs that the platform supports. |
| 215 | // |
| 216 | UINT32 NumberOfCpus; |
| 217 | // |
| 218 | // Physical address of structure of type MTRR_SETTINGS that contains a copy |
| 219 | // of the MTRR settings that are compatible with the MTRR settings used by |
| 220 | // the boot processor when the platform was booted. These MTRR settings are |
| 221 | // used during an ACPI S3 resume. |
| 222 | // |
| 223 | EFI_PHYSICAL_ADDRESS MtrrTable; |
| 224 | // |
| 225 | // Physical address of a buffer that contains the machine check handler that |
| 226 | // is used during an ACPI S3 Resume. In order for this machine check |
| 227 | // handler to be active on an AP during an ACPI S3 resume, the machine check |
| 228 | // vector in the IDT provided by IdtrProfile must be initialized to transfer |
| 229 | // control to this physical address. |
| 230 | // |
| 231 | EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase; |
| 232 | // |
| 233 | // The size, in bytes, of the machine check handler that is used during an |
| 234 | // ACPI S3 Resume. If this field is 0, then a machine check handler is not |
| 235 | // provided. |
| 236 | // |
| 237 | UINT32 ApMachineCheckHandlerSize; |
| 238 | // |
| 239 | // Data structure that is used for CPU feature initialization during ACPI S3 |
| 240 | // resume. |
| 241 | // |
| 242 | CPU_FEATURE_INIT_DATA CpuFeatureInitData; |
| 243 | } ACPI_CPU_DATA; |
| 244 | |
| 245 | #endif |