Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 1ae366f071852ea3a3fd50aa23d1448ad57d0fb3 / . / src / vendorcode / intel / edk2 / edk2-stable202302 / MdePkg / Include / Register / Intel / StmResourceDescriptor.h
blob: 5a1196888af6a571aaf9f917ffe082556e2c9299 [file] [log] [blame]
Ronak Kanabar1ae366f2023-06-07 01:21:56 +0530[diff] [blame^]1/** @file
2 STM Resource Descriptor
3
4 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 @par Specification Reference:
8 SMI Transfer Monitor (STM) User Guide Revision 1.00
9
10**/
11
12#ifndef _INTEL_STM_RESOURCE_DESCRIPTOR_H_
13#define _INTEL_STM_RESOURCE_DESCRIPTOR_H_
14
15#pragma pack (1)
16
17/**
18 STM Resource Descriptor Header
19**/
20typedef struct {
21 UINT32 RscType;
22 UINT16 Length;
23 UINT16 ReturnStatus : 1;
24 UINT16 Reserved : 14;
25 UINT16 IgnoreResource : 1;
26} STM_RSC_DESC_HEADER;
27
28/**
29 Define values for the RscType field of #STM_RSC_DESC_HEADER
30 @{
31**/
32#define END_OF_RESOURCES 0
33#define MEM_RANGE 1
34#define IO_RANGE 2
35#define MMIO_RANGE 3
36#define MACHINE_SPECIFIC_REG 4
37#define PCI_CFG_RANGE 5
38#define TRAPPED_IO_RANGE 6
39#define ALL_RESOURCES 7
40#define REGISTER_VIOLATION 8
41#define MAX_DESC_TYPE 8
42/// @}
43
44/**
45 STM Resource End Descriptor
46**/
47typedef struct {
48 STM_RSC_DESC_HEADER Hdr;
49 UINT64 ResourceListContinuation;
50} STM_RSC_END;
51
52/**
53 STM Resource Memory Descriptor
54**/
55typedef struct {
56 STM_RSC_DESC_HEADER Hdr;
57 UINT64 Base;
58 UINT64 Length;
59 UINT32 RWXAttributes : 3;
60 UINT32 Reserved : 29;
61 UINT32 Reserved_2;
62} STM_RSC_MEM_DESC;
63
64/**
65 Define values for the RWXAttributes field of #STM_RSC_MEM_DESC
66 @{
67**/
68#define STM_RSC_MEM_R 0x1
69#define STM_RSC_MEM_W 0x2
70#define STM_RSC_MEM_X 0x4
71/// @}
72
73/**
74 STM Resource I/O Descriptor
75**/
76typedef struct {
77 STM_RSC_DESC_HEADER Hdr;
78 UINT16 Base;
79 UINT16 Length;
80 UINT32 Reserved;
81} STM_RSC_IO_DESC;
82
83/**
84 STM Resource MMIO Descriptor
85**/
86typedef struct {
87 STM_RSC_DESC_HEADER Hdr;
88 UINT64 Base;
89 UINT64 Length;
90 UINT32 RWXAttributes : 3;
91 UINT32 Reserved : 29;
92 UINT32 Reserved_2;
93} STM_RSC_MMIO_DESC;
94
95/**
96 Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC
97 @{
98**/
99#define STM_RSC_MMIO_R 0x1
100#define STM_RSC_MMIO_W 0x2
101#define STM_RSC_MMIO_X 0x4
102/// @}
103
104/**
105 STM Resource MSR Descriptor
106**/
107typedef struct {
108 STM_RSC_DESC_HEADER Hdr;
109 UINT32 MsrIndex;
110 UINT32 KernelModeProcessing : 1;
111 UINT32 Reserved : 31;
112 UINT64 ReadMask;
113 UINT64 WriteMask;
114} STM_RSC_MSR_DESC;
115
116/**
117 STM PCI Device Path node used for the PciDevicePath field of
118 #STM_RSC_PCI_CFG_DESC
119**/
120typedef struct {
121 ///
122 /// Must be 1, indicating Hardware Device Path
123 ///
124 UINT8 Type;
125 ///
126 /// Must be 1, indicating PCI
127 ///
128 UINT8 Subtype;
129 ///
130 /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6
131 ///
132 UINT16 Length;
133 UINT8 PciFunction;
134 UINT8 PciDevice;
135} STM_PCI_DEVICE_PATH_NODE;
136
137/**
138 STM Resource PCI Configuration Descriptor
139**/
140typedef struct {
141 STM_RSC_DESC_HEADER Hdr;
142 UINT16 RWAttributes : 2;
143 UINT16 Reserved : 14;
144 UINT16 Base;
145 UINT16 Length;
146 UINT8 OriginatingBusNumber;
147 UINT8 LastNodeIndex;
148 STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];
149 // STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];
150} STM_RSC_PCI_CFG_DESC;
151
152/**
153 Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC
154 @{
155**/
156#define STM_RSC_PCI_CFG_R 0x1
157#define STM_RSC_PCI_CFG_W 0x2
158/// @}
159
160/**
161 STM Resource Trapped I/O Descriptor
162**/
163typedef struct {
164 STM_RSC_DESC_HEADER Hdr;
165 UINT16 Base;
166 UINT16 Length;
167 UINT16 In : 1;
168 UINT16 Out : 1;
169 UINT16 Api : 1;
170 UINT16 Reserved1 : 13;
171 UINT16 Reserved2;
172} STM_RSC_TRAPPED_IO_DESC;
173
174/**
175 STM Resource All Descriptor
176**/
177typedef struct {
178 STM_RSC_DESC_HEADER Hdr;
179} STM_RSC_ALL_RESOURCES_DESC;
180
181/**
182 STM Register Violation Descriptor
183**/
184typedef struct {
185 STM_RSC_DESC_HEADER Hdr;
186 UINT32 RegisterType;
187 UINT32 Reserved;
188 UINT64 ReadMask;
189 UINT64 WriteMask;
190} STM_REGISTER_VIOLATION_DESC;
191
192/**
193 Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC
194**/
195typedef enum {
196 StmRegisterCr0,
197 StmRegisterCr2,
198 StmRegisterCr3,
199 StmRegisterCr4,
200 StmRegisterCr8,
201 StmRegisterMax,
202} STM_REGISTER_VIOLATION_TYPE;
203
204/**
205 Union of all STM resource types
206**/
207typedef union {
208 STM_RSC_DESC_HEADER Header;
209 STM_RSC_END End;
210 STM_RSC_MEM_DESC Mem;
211 STM_RSC_IO_DESC Io;
212 STM_RSC_MMIO_DESC Mmio;
213 STM_RSC_MSR_DESC Msr;
214 STM_RSC_PCI_CFG_DESC PciCfg;
215 STM_RSC_TRAPPED_IO_DESC TrappedIo;
216 STM_RSC_ALL_RESOURCES_DESC All;
217 STM_REGISTER_VIOLATION_DESC RegisterViolation;
218} STM_RSC;
219
220#pragma pack ()
221
222#endif